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[PULL 29/29] target/arm: Restrict arm_cpu_exec_interrupt() to TCG accele
From: |
Peter Maydell |
Subject: |
[PULL 29/29] target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator |
Date: |
Thu, 15 Dec 2022 12:50:09 +0000 |
From: Philippe Mathieu-Daudé <philmd@linaro.org>
When building with --disable-tcg on Darwin we get:
target/arm/cpu.c:725:16: error: incomplete definition of type 'struct
TCGCPUOps'
cc->tcg_ops->do_interrupt(cs);
~~~~~~~~~~~^
Commit 083afd18a9 ("target/arm: Restrict cpu_exec_interrupt()
handler to sysemu") limited this block to system emulation,
but neglected to also limit it to TCG.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Message-id: 20221209110823.59495-1-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 38d066c294d..0f55004d7e7 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -528,7 +528,7 @@ static void arm_cpu_reset(DeviceState *dev)
arm_rebuild_hflags(env);
}
-#ifndef CONFIG_USER_ONLY
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
unsigned int target_el,
@@ -725,7 +725,8 @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
cc->tcg_ops->do_interrupt(cs);
return true;
}
-#endif /* !CONFIG_USER_ONLY */
+
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
void arm_cpu_update_virq(ARMCPU *cpu)
{
--
2.25.1
- [PULL 11/29] target/arm: Allow relevant HCR bits to be written for FEAT_EVT, (continued)
- [PULL 11/29] target/arm: Allow relevant HCR bits to be written for FEAT_EVT, Peter Maydell, 2022/12/15
- [PULL 10/29] hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement, Peter Maydell, 2022/12/15
- [PULL 12/29] target/arm: Implement HCR_EL2.TTLBIS traps, Peter Maydell, 2022/12/15
- [PULL 13/29] target/arm: Implement HCR_EL2.TTLBOS traps, Peter Maydell, 2022/12/15
- [PULL 15/29] target/arm: Implement HCR_EL2.TID4 traps, Peter Maydell, 2022/12/15
- [PULL 17/29] hw/arm: Convert TYPE_ARM_SMMU to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 14/29] target/arm: Implement HCR_EL2.TICAB,TOCU traps, Peter Maydell, 2022/12/15
- [PULL 21/29] hw/intc: Convert TYPE_ARM_GICV3_COMMON to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 19/29] hw/intc: Convert TYPE_ARM_GIC_COMMON to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 08/29] hw/arm/virt: build SMBIOS 19 table, Peter Maydell, 2022/12/15
- [PULL 29/29] target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator,
Peter Maydell <=
- [PULL 22/29] hw/intc: Convert TYPE_KVM_ARM_GICV3 to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 23/29] hw/intc: Convert TYPE_ARM_GICV3_ITS_COMMON to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 28/29] hw/misc: Move some arm-related files from specific_ss into softmmu_ss, Peter Maydell, 2022/12/15
- [PULL 25/29] hw/intc: Convert TYPE_KVM_ARM_ITS to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 18/29] hw/arm: Convert TYPE_ARM_SMMUV3 to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 16/29] target/arm: Report FEAT_EVT for TCG '-cpu max', Peter Maydell, 2022/12/15
- [PULL 20/29] hw/intc: Convert TYPE_ARM_GIC_KVM to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 24/29] hw/intc: Convert TYPE_ARM_GICV3_ITS to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 26/29] hw/arm/boot: set initrd with #address-cells type in fdt, Peter Maydell, 2022/12/15
- [PULL 27/29] target/arm: align exposed ID registers with Linux, Peter Maydell, 2022/12/15