[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 14/29] target/arm: Implement HCR_EL2.TICAB,TOCU traps
From: |
Peter Maydell |
Subject: |
[PULL 14/29] target/arm: Implement HCR_EL2.TICAB,TOCU traps |
Date: |
Thu, 15 Dec 2022 12:49:54 +0000 |
For FEAT_EVT, the HCR_EL2.TICAB bit allows trapping of the ICIALLUIS
and IC IALLUIS cache maintenance instructions.
The HCR_EL2.TOCU bit traps all the other cache maintenance
instructions that operate to the point of unification:
AArch64 IC IVAU, IC IALLU, DC CVAU
AArch32 ICIMVAU, ICIALLU, DCCMVAU
The two trap bits between them cover all of the cache maintenance
instructions which must also check the HCR_TPU flag. Turn the old
aa64_cacheop_pou_access() function into a helper function which takes
the set of HCR_EL2 flags to check as an argument, and call it from
new access_ticab() and access_tocu() functions as appropriate for
each cache op.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.c | 36 +++++++++++++++++++++++-------------
1 file changed, 23 insertions(+), 13 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 0ec1c3ffbd6..eee95a42f7f 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4273,9 +4273,7 @@ static CPAccessResult aa64_cacheop_poc_access(CPUARMState
*env,
return CP_ACCESS_OK;
}
-static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env,
- const ARMCPRegInfo *ri,
- bool isread)
+static CPAccessResult do_cacheop_pou_access(CPUARMState *env, uint64_t
hcrflags)
{
/* Cache invalidate/clean to Point of Unification... */
switch (arm_current_el(env)) {
@@ -4286,8 +4284,8 @@ static CPAccessResult aa64_cacheop_pou_access(CPUARMState
*env,
}
/* fall through */
case 1:
- /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */
- if (arm_hcr_el2_eff(env) & HCR_TPU) {
+ /* ... EL1 must trap to EL2 if relevant HCR_EL2 flags are set. */
+ if (arm_hcr_el2_eff(env) & hcrflags) {
return CP_ACCESS_TRAP_EL2;
}
break;
@@ -4295,6 +4293,18 @@ static CPAccessResult
aa64_cacheop_pou_access(CPUARMState *env,
return CP_ACCESS_OK;
}
+static CPAccessResult access_ticab(CPUARMState *env, const ARMCPRegInfo *ri,
+ bool isread)
+{
+ return do_cacheop_pou_access(env, HCR_TICAB | HCR_TPU);
+}
+
+static CPAccessResult access_tocu(CPUARMState *env, const ARMCPRegInfo *ri,
+ bool isread)
+{
+ return do_cacheop_pou_access(env, HCR_TOCU | HCR_TPU);
+}
+
/* See: D4.7.2 TLB maintenance requirements and the TLB maintenance
instructions
* Page D4-1736 (DDI0487A.b)
*/
@@ -4935,15 +4945,15 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
.access = PL1_W, .type = ARM_CP_NOP,
- .accessfn = aa64_cacheop_pou_access },
+ .accessfn = access_ticab },
{ .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
.access = PL1_W, .type = ARM_CP_NOP,
- .accessfn = aa64_cacheop_pou_access },
+ .accessfn = access_tocu },
{ .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
.access = PL0_W, .type = ARM_CP_NOP,
- .accessfn = aa64_cacheop_pou_access },
+ .accessfn = access_tocu },
{ .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
.access = PL1_W, .accessfn = aa64_cacheop_poc_access,
@@ -4961,7 +4971,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
.access = PL0_W, .type = ARM_CP_NOP,
- .accessfn = aa64_cacheop_pou_access },
+ .accessfn = access_tocu },
{ .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
.access = PL0_W, .type = ARM_CP_NOP,
@@ -5138,13 +5148,13 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.writefn = tlbiipas2is_hyp_write },
/* 32 bit cache operations */
{ .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
- .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access
},
+ .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_ticab },
{ .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
.type = ARM_CP_NOP, .access = PL1_W },
{ .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
- .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access
},
+ .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu },
{ .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
- .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access
},
+ .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu },
{ .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
.type = ARM_CP_NOP, .access = PL1_W },
{ .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
@@ -5158,7 +5168,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
{ .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
- .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access
},
+ .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu },
{ .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access
},
{ .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
--
2.25.1
- [PULL 05/29] hw/arm/virt: Improve high memory region address assignment, (continued)
- [PULL 05/29] hw/arm/virt: Improve high memory region address assignment, Peter Maydell, 2022/12/15
- [PULL 07/29] hw/arm/virt: Add properties to disable high memory regions, Peter Maydell, 2022/12/15
- [PULL 02/29] hw/arm/virt: Rename variable size to region_size in virt_set_high_memmap(), Peter Maydell, 2022/12/15
- [PULL 09/29] target/arm: Add Cortex-A55 CPU, Peter Maydell, 2022/12/15
- [PULL 11/29] target/arm: Allow relevant HCR bits to be written for FEAT_EVT, Peter Maydell, 2022/12/15
- [PULL 10/29] hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement, Peter Maydell, 2022/12/15
- [PULL 12/29] target/arm: Implement HCR_EL2.TTLBIS traps, Peter Maydell, 2022/12/15
- [PULL 13/29] target/arm: Implement HCR_EL2.TTLBOS traps, Peter Maydell, 2022/12/15
- [PULL 15/29] target/arm: Implement HCR_EL2.TID4 traps, Peter Maydell, 2022/12/15
- [PULL 17/29] hw/arm: Convert TYPE_ARM_SMMU to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 14/29] target/arm: Implement HCR_EL2.TICAB,TOCU traps,
Peter Maydell <=
- [PULL 21/29] hw/intc: Convert TYPE_ARM_GICV3_COMMON to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 19/29] hw/intc: Convert TYPE_ARM_GIC_COMMON to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 08/29] hw/arm/virt: build SMBIOS 19 table, Peter Maydell, 2022/12/15
- [PULL 29/29] target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator, Peter Maydell, 2022/12/15
- [PULL 22/29] hw/intc: Convert TYPE_KVM_ARM_GICV3 to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 23/29] hw/intc: Convert TYPE_ARM_GICV3_ITS_COMMON to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 28/29] hw/misc: Move some arm-related files from specific_ss into softmmu_ss, Peter Maydell, 2022/12/15
- [PULL 25/29] hw/intc: Convert TYPE_KVM_ARM_ITS to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 18/29] hw/arm: Convert TYPE_ARM_SMMUV3 to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 16/29] target/arm: Report FEAT_EVT for TCG '-cpu max', Peter Maydell, 2022/12/15