[RFC PATCH 06/43] target/loongarch: Implement vaddi/vsubi

[Song Gao]

This patch includes:
- VADDI.{B/H/W/D}U;
- VSUBI.{B/H/W/D}U.

Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 target/loongarch/disas.c                    | 14 +++++
 target/loongarch/helper.h                   |  9 +++
 target/loongarch/insn_trans/trans_lsx.c.inc | 21 +++++++
 target/loongarch/insns.decode               | 11 ++++
 target/loongarch/lsx_helper.c               | 67 +++++++++++++++++++++
 5 files changed, 122 insertions(+)

diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 51c597603e..13a503951a 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -768,6 +768,11 @@ static void output_vvv(DisasContext *ctx, arg_vvv *a, 
const char *mnemonic)
     output(ctx, mnemonic, "v%d, v%d, v%d", a->vd, a->vj, a->vk);
 }
 
+static void output_vv_i(DisasContext *ctx, arg_vv_i *a, const char *mnemonic)
+{
+    output(ctx, mnemonic, "v%d, v%d, 0x%x", a->vd, a->vj, a->imm);
+}
+
 INSN_LSX(vadd_b,           vvv)
 INSN_LSX(vadd_h,           vvv)
 INSN_LSX(vadd_w,           vvv)
@@ -778,3 +783,12 @@ INSN_LSX(vsub_h,           vvv)
 INSN_LSX(vsub_w,           vvv)
 INSN_LSX(vsub_d,           vvv)
 INSN_LSX(vsub_q,           vvv)
+
+INSN_LSX(vaddi_bu,         vv_i)
+INSN_LSX(vaddi_hu,         vv_i)
+INSN_LSX(vaddi_wu,         vv_i)
+INSN_LSX(vaddi_du,         vv_i)
+INSN_LSX(vsubi_bu,         vv_i)
+INSN_LSX(vsubi_hu,         vv_i)
+INSN_LSX(vsubi_wu,         vv_i)
+INSN_LSX(vsubi_du,         vv_i)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 465bc36cb8..d6d50f6771 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -142,3 +142,12 @@ DEF_HELPER_4(vsub_h, void, env, i32, i32, i32)
 DEF_HELPER_4(vsub_w, void, env, i32, i32, i32)
 DEF_HELPER_4(vsub_d, void, env, i32, i32, i32)
 DEF_HELPER_4(vsub_q, void, env, i32, i32, i32)
+
+DEF_HELPER_4(vaddi_bu, void, env, i32, i32, i32)
+DEF_HELPER_4(vaddi_hu, void, env, i32, i32, i32)
+DEF_HELPER_4(vaddi_wu, void, env, i32, i32, i32)
+DEF_HELPER_4(vaddi_du, void, env, i32, i32, i32)
+DEF_HELPER_4(vsubi_bu, void, env, i32, i32, i32)
+DEF_HELPER_4(vsubi_hu, void, env, i32, i32, i32)
+DEF_HELPER_4(vsubi_wu, void, env, i32, i32, i32)
+DEF_HELPER_4(vsubi_du, void, env, i32, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc 
b/target/loongarch/insn_trans/trans_lsx.c.inc
index b2276ae688..9485a03a08 100644
--- a/target/loongarch/insn_trans/trans_lsx.c.inc
+++ b/target/loongarch/insn_trans/trans_lsx.c.inc
@@ -27,6 +27,18 @@ static bool gen_vvv(DisasContext *ctx, arg_vvv *a,
     return true;
 }
 
+static bool gen_vv_i(DisasContext *ctx, arg_vv_i *a,
+                     void (*func)(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32))
+{
+    TCGv_i32 vd = tcg_constant_i32(a->vd);
+    TCGv_i32 vj = tcg_constant_i32(a->vj);
+    TCGv_i32 imm = tcg_constant_i32(a->imm);
+
+    CHECK_SXE;
+    func(cpu_env, vd, vj, imm);
+    return true;
+}
+
 TRANS(vadd_b, gen_vvv, gen_helper_vadd_b)
 TRANS(vadd_h, gen_vvv, gen_helper_vadd_h)
 TRANS(vadd_w, gen_vvv, gen_helper_vadd_w)
@@ -37,3 +49,12 @@ TRANS(vsub_h, gen_vvv, gen_helper_vsub_h)
 TRANS(vsub_w, gen_vvv, gen_helper_vsub_w)
 TRANS(vsub_d, gen_vvv, gen_helper_vsub_d)
 TRANS(vsub_q, gen_vvv, gen_helper_vsub_q)
+
+TRANS(vaddi_bu, gen_vv_i, gen_helper_vaddi_bu)
+TRANS(vaddi_hu, gen_vv_i, gen_helper_vaddi_hu)
+TRANS(vaddi_wu, gen_vv_i, gen_helper_vaddi_wu)
+TRANS(vaddi_du, gen_vv_i, gen_helper_vaddi_du)
+TRANS(vsubi_bu, gen_vv_i, gen_helper_vsubi_bu)
+TRANS(vsubi_hu, gen_vv_i, gen_helper_vsubi_hu)
+TRANS(vsubi_wu, gen_vv_i, gen_helper_vsubi_wu)
+TRANS(vsubi_du, gen_vv_i, gen_helper_vsubi_du)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 0dd6ab20a2..4f8226060a 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -490,11 +490,13 @@ dbcl             0000 00000010 10101 ...............      
@i15
 #
 
 &vvv          vd vj vk
+&vv_i         vd vj imm
 
 #
 # LSX Formats
 #
 @vvv               .... ........ ..... vk:5 vj:5 vd:5    &vvv
+@vv_ui5           .... ........ ..... imm:5 vj:5 vd:5    &vv_i
 
 vadd_b           0111 00000000 10100 ..... ..... .....    @vvv
 vadd_h           0111 00000000 10101 ..... ..... .....    @vvv
@@ -506,3 +508,12 @@ vsub_h           0111 00000000 11001 ..... ..... .....    
@vvv
 vsub_w           0111 00000000 11010 ..... ..... .....    @vvv
 vsub_d           0111 00000000 11011 ..... ..... .....    @vvv
 vsub_q           0111 00010010 11011 ..... ..... .....    @vvv
+
+vaddi_bu         0111 00101000 10100 ..... ..... .....    @vv_ui5
+vaddi_hu         0111 00101000 10101 ..... ..... .....    @vv_ui5
+vaddi_wu         0111 00101000 10110 ..... ..... .....    @vv_ui5
+vaddi_du         0111 00101000 10111 ..... ..... .....    @vv_ui5
+vsubi_bu         0111 00101000 11000 ..... ..... .....    @vv_ui5
+vsubi_hu         0111 00101000 11001 ..... ..... .....    @vv_ui5
+vsubi_wu         0111 00101000 11010 ..... ..... .....    @vv_ui5
+vsubi_du         0111 00101000 11011 ..... ..... .....    @vv_ui5
diff --git a/target/loongarch/lsx_helper.c b/target/loongarch/lsx_helper.c
index 195b2ffa8d..e227db20d3 100644
--- a/target/loongarch/lsx_helper.c
+++ b/target/loongarch/lsx_helper.c
@@ -15,6 +15,11 @@
                        uint32_t vd, uint32_t vj, uint32_t vk) \
     { FUNC(env, vd, vj, vk, BIT, __VA_ARGS__); }
 
+#define DO_HELPER_VV_I(NAME, BIT, FUNC, ...)                   \
+    void helper_##NAME(CPULoongArchState *env,                 \
+                       uint32_t vd, uint32_t vj, uint32_t imm) \
+    { FUNC(env, vd, vj, imm, BIT, __VA_ARGS__ ); }
+
 static void helper_vvv(CPULoongArchState *env,
                        uint32_t vd, uint32_t vj, uint32_t vk, int bit,
                        void (*func)(vec_t*, vec_t*, vec_t*, int, int))
@@ -29,6 +34,19 @@ static void helper_vvv(CPULoongArchState *env,
     }
 }
 
+static  void helper_vv_i(CPULoongArchState *env,
+                         uint32_t vd, uint32_t vj, uint32_t imm, int bit,
+                         void (*func)(vec_t*, vec_t*, uint32_t, int, int))
+{
+    int i;
+    vec_t *Vd = &(env->fpr[vd].vec);
+    vec_t *Vj = &(env->fpr[vj].vec);
+
+    for (i = 0; i < LSX_LEN/bit; i++) {
+        func(Vd, Vj, imm, bit, i);
+    }
+}
+
 static void do_vadd(vec_t *Vd, vec_t *Vj, vec_t *Vk,  int bit, int n)
 {
     switch (bit) {
@@ -85,3 +103,52 @@ DO_HELPER_VVV(vsub_h, 16, helper_vvv, do_vsub)
 DO_HELPER_VVV(vsub_w, 32, helper_vvv, do_vsub)
 DO_HELPER_VVV(vsub_d, 64, helper_vvv, do_vsub)
 DO_HELPER_VVV(vsub_q, 128, helper_vvv, do_vsub)
+
+static void do_vaddi(vec_t *Vd, vec_t *Vj, uint32_t imm, int bit, int n)
+{
+    switch (bit) {
+    case 8:
+        Vd->B[n] = Vj->B[n] + imm;
+        break;
+    case 16:
+        Vd->H[n] = Vj->H[n] + imm;
+        break;
+    case 32:
+        Vd->W[n] = Vj->W[n] + imm;
+        break;
+    case 64:
+        Vd->D[n] = Vj->D[n] + imm;
+        break;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static void do_vsubi(vec_t *Vd, vec_t *Vj, uint32_t imm, int bit, int n)
+{
+    switch (bit) {
+    case 8:
+        Vd->B[n] = Vj->B[n] - imm;
+        break;
+    case 16:
+        Vd->H[n] = Vj->H[n] - imm;
+        break;
+    case 32:
+        Vd->W[n] = Vj->W[n] - imm;
+        break;
+    case 64:
+        Vd->D[n] = Vd->D[n] - imm;
+        break;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+DO_HELPER_VV_I(vaddi_bu, 8, helper_vv_i, do_vaddi)
+DO_HELPER_VV_I(vaddi_hu, 16, helper_vv_i, do_vaddi)
+DO_HELPER_VV_I(vaddi_wu, 32, helper_vv_i, do_vaddi)
+DO_HELPER_VV_I(vaddi_du, 64, helper_vv_i, do_vaddi)
+DO_HELPER_VV_I(vsubi_bu, 8, helper_vv_i, do_vsubi)
+DO_HELPER_VV_I(vsubi_hu, 16, helper_vv_i, do_vsubi)
+DO_HELPER_VV_I(vsubi_wu, 32, helper_vv_i, do_vsubi)
+DO_HELPER_VV_I(vsubi_du, 64, helper_vv_i, do_vsubi)
-- 
2.31.1