[RFC PATCH 30/43] target/loongarch: Implement vclo vclz

[Song Gao]

This patch includes:
- VCLO.{B/H/W/D};
- VCLZ.{B/H/W/D}.

Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 target/loongarch/disas.c                    |  9 ++++
 target/loongarch/helper.h                   |  9 ++++
 target/loongarch/insn_trans/trans_lsx.c.inc |  9 ++++
 target/loongarch/insns.decode               |  9 ++++
 target/loongarch/lsx_helper.c               | 49 +++++++++++++++++++++
 5 files changed, 85 insertions(+)

diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index c1d256d8b4..865c293f43 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1229,3 +1229,12 @@ INSN_LSX(vssrarni_bu_h,    vv_i)
 INSN_LSX(vssrarni_hu_w,    vv_i)
 INSN_LSX(vssrarni_wu_d,    vv_i)
 INSN_LSX(vssrarni_du_q,    vv_i)
+
+INSN_LSX(vclo_b,           vv)
+INSN_LSX(vclo_h,           vv)
+INSN_LSX(vclo_w,           vv)
+INSN_LSX(vclo_d,           vv)
+INSN_LSX(vclz_b,           vv)
+INSN_LSX(vclz_h,           vv)
+INSN_LSX(vclz_w,           vv)
+INSN_LSX(vclz_d,           vv)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index e45eb211a6..0080890bf6 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -584,3 +584,12 @@ DEF_HELPER_4(vssrarni_bu_h, void, env, i32, i32, i32)
 DEF_HELPER_4(vssrarni_hu_w, void, env, i32, i32, i32)
 DEF_HELPER_4(vssrarni_wu_d, void, env, i32, i32, i32)
 DEF_HELPER_4(vssrarni_du_q, void, env, i32, i32, i32)
+
+DEF_HELPER_3(vclo_b, void, env, i32, i32)
+DEF_HELPER_3(vclo_h, void, env, i32, i32)
+DEF_HELPER_3(vclo_w, void, env, i32, i32)
+DEF_HELPER_3(vclo_d, void, env, i32, i32)
+DEF_HELPER_3(vclz_b, void, env, i32, i32)
+DEF_HELPER_3(vclz_h, void, env, i32, i32)
+DEF_HELPER_3(vclz_w, void, env, i32, i32)
+DEF_HELPER_3(vclz_d, void, env, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc 
b/target/loongarch/insn_trans/trans_lsx.c.inc
index 5473adc163..105b6fac6e 100644
--- a/target/loongarch/insn_trans/trans_lsx.c.inc
+++ b/target/loongarch/insn_trans/trans_lsx.c.inc
@@ -500,3 +500,12 @@ TRANS(vssrarni_bu_h, gen_vv_i, gen_helper_vssrarni_bu_h)
 TRANS(vssrarni_hu_w, gen_vv_i, gen_helper_vssrarni_hu_w)
 TRANS(vssrarni_wu_d, gen_vv_i, gen_helper_vssrarni_wu_d)
 TRANS(vssrarni_du_q, gen_vv_i, gen_helper_vssrarni_du_q)
+
+TRANS(vclo_b, gen_vv, gen_helper_vclo_b)
+TRANS(vclo_h, gen_vv, gen_helper_vclo_h)
+TRANS(vclo_w, gen_vv, gen_helper_vclo_w)
+TRANS(vclo_d, gen_vv, gen_helper_vclo_d)
+TRANS(vclz_b, gen_vv, gen_helper_vclz_b)
+TRANS(vclz_h, gen_vv, gen_helper_vclz_h)
+TRANS(vclz_w, gen_vv, gen_helper_vclz_w)
+TRANS(vclz_d, gen_vv, gen_helper_vclz_d)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 3b3c2520c3..27cfa306c9 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -958,3 +958,12 @@ vssrarni_bu_h    0111 00110110 11000 1 .... ..... .....   
@vv_ui4
 vssrarni_hu_w    0111 00110110 11001 ..... ..... .....    @vv_ui5
 vssrarni_wu_d    0111 00110110 1101 ...... ..... .....    @vv_ui6
 vssrarni_du_q    0111 00110110 111 ....... ..... .....    @vv_ui7
+
+vclo_b           0111 00101001 11000 00000 ..... .....    @vv
+vclo_h           0111 00101001 11000 00001 ..... .....    @vv
+vclo_w           0111 00101001 11000 00010 ..... .....    @vv
+vclo_d           0111 00101001 11000 00011 ..... .....    @vv
+vclz_b           0111 00101001 11000 00100 ..... .....    @vv
+vclz_h           0111 00101001 11000 00101 ..... .....    @vv
+vclz_w           0111 00101001 11000 00110 ..... .....    @vv
+vclz_d           0111 00101001 11000 00111 ..... .....    @vv
diff --git a/target/loongarch/lsx_helper.c b/target/loongarch/lsx_helper.c
index d771ff953c..0abb06781f 100644
--- a/target/loongarch/lsx_helper.c
+++ b/target/loongarch/lsx_helper.c
@@ -3148,3 +3148,52 @@ DO_HELPER_VV_I(vssrarni_bu_h, 16, helper_vv_ni_c, 
do_vssrarni_u)
 DO_HELPER_VV_I(vssrarni_hu_w, 32, helper_vv_ni_c, do_vssrarni_u)
 DO_HELPER_VV_I(vssrarni_wu_d, 64, helper_vv_ni_c, do_vssrarni_u)
 DO_HELPER_VV_I(vssrarni_du_q, 128, helper_vv_ni_c, do_vssrarni_u)
+
+static void do_vclo(vec_t *Vd, vec_t *Vj, int bit, int n)
+{
+    switch (bit) {
+    case 8:
+        Vd->B[n] = clz32((uint8_t)(~Vj->B[n])) - 24;
+        break;
+    case 16:
+        Vd->H[n] = clz32((uint16_t)(~Vj->H[n])) - 16;
+        break;
+    case 32:
+        Vd->W[n] = clz32((uint32_t)(~Vj->W[n]));
+        break;
+    case 64:
+        Vd->D[n] = clz64((uint64_t)(~Vj->D[n]));
+        break;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static void do_vclz(vec_t *Vd, vec_t *Vj, int bit, int n)
+{
+    switch (bit) {
+    case 8:
+        Vd->B[n] = clz32((uint8_t)Vj->B[n]) - 24;
+        break;
+    case 16:
+        Vd->H[n] = clz32((uint16_t)Vj->H[n]) - 16;
+        break;
+    case 32:
+        Vd->W[n] = clz32((uint32_t)Vj->W[n]);
+        break;
+    case 64:
+        Vd->D[n] = clz64((uint64_t)Vj->D[n]);
+        break;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+DO_HELPER_VV(vclo_b, 8, helper_vv, do_vclo)
+DO_HELPER_VV(vclo_h, 16, helper_vv, do_vclo)
+DO_HELPER_VV(vclo_w, 32, helper_vv, do_vclo)
+DO_HELPER_VV(vclo_d, 64, helper_vv, do_vclo)
+DO_HELPER_VV(vclz_b, 8, helper_vv, do_vclz)
+DO_HELPER_VV(vclz_h, 16, helper_vv, do_vclz)
+DO_HELPER_VV(vclz_w, 32, helper_vv, do_vclz)
+DO_HELPER_VV(vclz_d, 64, helper_vv, do_vclz)
-- 
2.31.1