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[PULL 28/29] hw/misc: In STM32L4x5 EXTI, correct configurable interrupts
From: |
Peter Maydell |
Subject: |
[PULL 28/29] hw/misc: In STM32L4x5 EXTI, correct configurable interrupts |
Date: |
Mon, 1 Jul 2024 17:07:28 +0100 |
From: Inès Varhol <ines.varhol@telecom-paris.fr>
The implementation of configurable interrupts (interrupts supporting
edge selection) was incorrectly expecting alternating input levels :
this commits adds a new status field `irq_levels` to actually detect
edges.
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Message-id: 20240629110800.539969-2-ines.varhol@telecom-paris.fr
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/misc/stm32l4x5_exti.h | 2 ++
hw/misc/stm32l4x5_exti.c | 28 +++++++++++++---------------
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/include/hw/misc/stm32l4x5_exti.h b/include/hw/misc/stm32l4x5_exti.h
index be961d2f01f..55f763fa376 100644
--- a/include/hw/misc/stm32l4x5_exti.h
+++ b/include/hw/misc/stm32l4x5_exti.h
@@ -45,6 +45,8 @@ struct Stm32l4x5ExtiState {
uint32_t swier[EXTI_NUM_REGISTER];
uint32_t pr[EXTI_NUM_REGISTER];
+ /* used for edge detection */
+ uint32_t irq_levels[EXTI_NUM_REGISTER];
qemu_irq irq[EXTI_NUM_INTERRUPT_OUT_LINES];
};
diff --git a/hw/misc/stm32l4x5_exti.c b/hw/misc/stm32l4x5_exti.c
index 495a0004ab4..6a2ec62d785 100644
--- a/hw/misc/stm32l4x5_exti.c
+++ b/hw/misc/stm32l4x5_exti.c
@@ -88,6 +88,7 @@ static void stm32l4x5_exti_reset_hold(Object *obj, ResetType
type)
s->ftsr[bank] = 0x00000000;
s->swier[bank] = 0x00000000;
s->pr[bank] = 0x00000000;
+ s->irq_levels[bank] = 0x00000000;
}
}
@@ -102,27 +103,23 @@ static void stm32l4x5_exti_set_irq(void *opaque, int irq,
int level)
/* Shift the value to enable access in x2 registers. */
irq %= EXTI_MAX_IRQ_PER_BANK;
+ if (level == extract32(s->irq_levels[bank], irq, 1)) {
+ /* No change in IRQ line state: do nothing */
+ return;
+ }
+ s->irq_levels[bank] = deposit32(s->irq_levels[bank], irq, 1, level);
+
/* If the interrupt is masked, pr won't be raised */
if (!extract32(s->imr[bank], irq, 1)) {
return;
}
- if (((1 << irq) & s->rtsr[bank]) && level) {
- /* Rising Edge */
- s->pr[bank] |= 1 << irq;
- qemu_irq_pulse(s->irq[oirq]);
- } else if (((1 << irq) & s->ftsr[bank]) && !level) {
- /* Falling Edge */
+ if ((level && extract32(s->rtsr[bank], irq, 1)) ||
+ (!level && extract32(s->ftsr[bank], irq, 1))) {
+
s->pr[bank] |= 1 << irq;
qemu_irq_pulse(s->irq[oirq]);
}
- /*
- * In the following situations :
- * - falling edge but rising trigger selected
- * - rising edge but falling trigger selected
- * - no trigger selected
- * No action is required
- */
}
static uint64_t stm32l4x5_exti_read(void *opaque, hwaddr addr,
@@ -255,8 +252,8 @@ static void stm32l4x5_exti_init(Object *obj)
static const VMStateDescription vmstate_stm32l4x5_exti = {
.name = TYPE_STM32L4X5_EXTI,
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(imr, Stm32l4x5ExtiState, EXTI_NUM_REGISTER),
VMSTATE_UINT32_ARRAY(emr, Stm32l4x5ExtiState, EXTI_NUM_REGISTER),
@@ -264,6 +261,7 @@ static const VMStateDescription vmstate_stm32l4x5_exti = {
VMSTATE_UINT32_ARRAY(ftsr, Stm32l4x5ExtiState, EXTI_NUM_REGISTER),
VMSTATE_UINT32_ARRAY(swier, Stm32l4x5ExtiState, EXTI_NUM_REGISTER),
VMSTATE_UINT32_ARRAY(pr, Stm32l4x5ExtiState, EXTI_NUM_REGISTER),
+ VMSTATE_UINT32_ARRAY(irq_levels, Stm32l4x5ExtiState,
EXTI_NUM_REGISTER),
VMSTATE_END_OF_LIST()
}
};
--
2.34.1
- [PULL 14/29] target/arm: Convert BFMLALB, BFMLALT to decodetree, (continued)
- [PULL 14/29] target/arm: Convert BFMLALB, BFMLALT to decodetree, Peter Maydell, 2024/07/01
- [PULL 06/29] hw/arm/smmu-common: Replace smmu_iommu_mr with smmu_find_sdev, Peter Maydell, 2024/07/01
- [PULL 21/29] target/arm: Move initialization of debug ID registers, Peter Maydell, 2024/07/01
- [PULL 11/29] target/arm: Convert SDOT, UDOT to decodetree, Peter Maydell, 2024/07/01
- [PULL 09/29] target/arm: Fix FJCVTZS vs flush-to-zero, Peter Maydell, 2024/07/01
- [PULL 16/29] target/arm: Add data argument to do_fp3_vector, Peter Maydell, 2024/07/01
- [PULL 22/29] target/arm: Enable FEAT_Debugv8p8 for -cpu max, Peter Maydell, 2024/07/01
- [PULL 19/29] target/arm: Delete dead code from disas_simd_indexed, Peter Maydell, 2024/07/01
- [PULL 24/29] hw/misc/zynq_slcr: Add boot-mode property, Peter Maydell, 2024/07/01
- [PULL 25/29] hw/arm/xilinx_zynq: Add boot-mode property, Peter Maydell, 2024/07/01
- [PULL 28/29] hw/misc: In STM32L4x5 EXTI, correct configurable interrupts,
Peter Maydell <=
- [PULL 12/29] target/arm: Convert SUDOT, USDOT to decodetree, Peter Maydell, 2024/07/01
- [PULL 13/29] target/arm: Convert BFDOT to decodetree, Peter Maydell, 2024/07/01
- [PULL 17/29] target/arm: Convert FCADD to decodetree, Peter Maydell, 2024/07/01
- [PULL 15/29] target/arm: Convert BFMMLA, SMMLA, UMMLA, USMMLA to decodetree, Peter Maydell, 2024/07/01
- [PULL 23/29] MAINTAINERS: Update my family name, Peter Maydell, 2024/07/01
- [PULL 20/29] target/arm: Fix indentation, Peter Maydell, 2024/07/01
- [PULL 27/29] tests/qtest: Fix STM32L4x5 SYSCFG irq line 15 state assumption, Peter Maydell, 2024/07/01
- [PULL 29/29] tests/qtest: Ensure STM32L4x5 EXTI state is correct at the end of QTests, Peter Maydell, 2024/07/01
- [PULL 18/29] target/arm: Convert FCMLA to decodetree, Peter Maydell, 2024/07/01
- Re: [PULL 00/29] target-arm queue, Richard Henderson, 2024/07/01