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[PULL 17/29] target/arm: Convert FCADD to decodetree
From: |
Peter Maydell |
Subject: |
[PULL 17/29] target/arm: Convert FCADD to decodetree |
Date: |
Mon, 1 Jul 2024 17:07:17 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240625183536.1672454-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/tcg/a64.decode | 3 +++
target/arm/tcg/translate-a64.c | 33 ++++++++++-----------------------
2 files changed, 13 insertions(+), 23 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index b2c7e36969e..f330919851b 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -957,6 +957,9 @@ SMMLA 0100 1110 100 ..... 10100 1 ..... .....
@rrr_q1e0
UMMLA 0110 1110 100 ..... 10100 1 ..... ..... @rrr_q1e0
USMMLA 0100 1110 100 ..... 10101 1 ..... ..... @rrr_q1e0
+FCADD_90 0.10 1110 ..0 ..... 11100 1 ..... ..... @qrrr_e
+FCADD_270 0.10 1110 ..0 ..... 11110 1 ..... ..... @qrrr_e
+
### Advanced SIMD scalar x indexed element
FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 57cdde008ef..a1b338263ff 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -5623,6 +5623,14 @@ static bool trans_BFMLAL_v(DisasContext *s, arg_qrrr_e
*a)
return true;
}
+static gen_helper_gvec_3_ptr * const f_vector_fcadd[3] = {
+ gen_helper_gvec_fcaddh,
+ gen_helper_gvec_fcadds,
+ gen_helper_gvec_fcaddd,
+};
+TRANS_FEAT(FCADD_90, aa64_fcma, do_fp3_vector, a, 0, f_vector_fcadd)
+TRANS_FEAT(FCADD_270, aa64_fcma, do_fp3_vector, a, 1, f_vector_fcadd)
+
/*
* Advanced SIMD scalar/vector x indexed element
*/
@@ -10957,8 +10965,6 @@ static void
disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
case 0x19: /* FCMLA, #90 */
case 0x1a: /* FCMLA, #180 */
case 0x1b: /* FCMLA, #270 */
- case 0x1c: /* FCADD, #90 */
- case 0x1e: /* FCADD, #270 */
if (size == 0
|| (size == 1 && !dc_isar_feature(aa64_fp16, s))
|| (size == 3 && !is_q)) {
@@ -10976,7 +10982,9 @@ static void
disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
case 0x11: /* SQRDMLSH (vector) */
case 0x12: /* UDOT (vector) */
case 0x14: /* UMMLA */
+ case 0x1c: /* FCADD, #90 */
case 0x1d: /* BFMMLA */
+ case 0x1e: /* FCADD, #270 */
case 0x1f: /* BFDOT / BFMLAL */
unallocated_encoding(s);
return;
@@ -11013,27 +11021,6 @@ static void
disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
}
return;
- case 0xc: /* FCADD, #90 */
- case 0xe: /* FCADD, #270 */
- rot = extract32(opcode, 1, 1);
- switch (size) {
- case 1:
- gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot,
- gen_helper_gvec_fcaddh);
- break;
- case 2:
- gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot,
- gen_helper_gvec_fcadds);
- break;
- case 3:
- gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot,
- gen_helper_gvec_fcaddd);
- break;
- default:
- g_assert_not_reached();
- }
- return;
-
default:
g_assert_not_reached();
}
--
2.34.1
- [PULL 11/29] target/arm: Convert SDOT, UDOT to decodetree, (continued)
- [PULL 11/29] target/arm: Convert SDOT, UDOT to decodetree, Peter Maydell, 2024/07/01
- [PULL 09/29] target/arm: Fix FJCVTZS vs flush-to-zero, Peter Maydell, 2024/07/01
- [PULL 16/29] target/arm: Add data argument to do_fp3_vector, Peter Maydell, 2024/07/01
- [PULL 22/29] target/arm: Enable FEAT_Debugv8p8 for -cpu max, Peter Maydell, 2024/07/01
- [PULL 19/29] target/arm: Delete dead code from disas_simd_indexed, Peter Maydell, 2024/07/01
- [PULL 24/29] hw/misc/zynq_slcr: Add boot-mode property, Peter Maydell, 2024/07/01
- [PULL 25/29] hw/arm/xilinx_zynq: Add boot-mode property, Peter Maydell, 2024/07/01
- [PULL 28/29] hw/misc: In STM32L4x5 EXTI, correct configurable interrupts, Peter Maydell, 2024/07/01
- [PULL 12/29] target/arm: Convert SUDOT, USDOT to decodetree, Peter Maydell, 2024/07/01
- [PULL 13/29] target/arm: Convert BFDOT to decodetree, Peter Maydell, 2024/07/01
- [PULL 17/29] target/arm: Convert FCADD to decodetree,
Peter Maydell <=
- [PULL 15/29] target/arm: Convert BFMMLA, SMMLA, UMMLA, USMMLA to decodetree, Peter Maydell, 2024/07/01
- [PULL 23/29] MAINTAINERS: Update my family name, Peter Maydell, 2024/07/01
- [PULL 20/29] target/arm: Fix indentation, Peter Maydell, 2024/07/01
- [PULL 27/29] tests/qtest: Fix STM32L4x5 SYSCFG irq line 15 state assumption, Peter Maydell, 2024/07/01
- [PULL 29/29] tests/qtest: Ensure STM32L4x5 EXTI state is correct at the end of QTests, Peter Maydell, 2024/07/01
- [PULL 18/29] target/arm: Convert FCMLA to decodetree, Peter Maydell, 2024/07/01
- Re: [PULL 00/29] target-arm queue, Richard Henderson, 2024/07/01