Re: [PATCH ats_vtd v5 03/22] intel_iommu: return page walk level even when the translation fails

[Yi Liu]

On 2024/7/2 13:52, CLEMENT MATHIEU--DRIF wrote:
> From: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
>
> We use this information in vtd_do_iommu_translate to populate the
> IOMMUTLBEntry and indicate the correct page mask. This prevents ATS
> devices from sending many useless translation requests when a megapage
> or gigapage iova is not mapped to a physical address.

you may move this patch prior to "[PATCH ats_vtd v5 22/22] intel_iommu: add 
support for ATS" or just merge to it since it's the "user" of this commit.

> Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
> ---
>   hw/i386/intel_iommu.c | 15 +++++++--------
>   1 file changed, 7 insertions(+), 8 deletions(-)
>
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index c6474ae735..98996ededc 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -2096,9 +2096,9 @@ static int vtd_iova_to_flpte(IntelIOMMUState *s, 
> VTDContextEntry *ce,
>                                uint32_t pasid)
>   {
>       dma_addr_t addr = vtd_get_iova_pgtbl_base(s, ce, pasid);
> -    uint32_t level = vtd_get_iova_level(s, ce, pasid);
>       uint32_t offset;
>       uint64_t flpte;
> +    *flpte_level = vtd_get_iova_level(s, ce, pasid);
>   
>       if (!vtd_iova_fl_check_canonical(s, iova, ce, pasid)) {
>           error_report_once("%s: detected non canonical IOVA (iova=0x%" PRIx64 
> ","
> @@ -2107,11 +2107,11 @@ static int vtd_iova_to_flpte(IntelIOMMUState *s, 
> VTDContextEntry *ce,
>       }
>   
>       while (true) {
> -        offset = vtd_iova_level_offset(iova, level);
> +        offset = vtd_iova_level_offset(iova, *flpte_level);
>           flpte = vtd_get_pte(addr, offset);
>   
>           if (flpte == (uint64_t)-1) {
> -            if (level == vtd_get_iova_level(s, ce, pasid)) {
> +            if (*flpte_level == vtd_get_iova_level(s, ce, pasid)) {
>                   /* Invalid programming of context-entry */
>                   return -VTD_FR_CONTEXT_ENTRY_INV;
>               } else {
> @@ -2128,11 +2128,11 @@ static int vtd_iova_to_flpte(IntelIOMMUState *s, 
> VTDContextEntry *ce,
>           if (is_write && !(flpte & VTD_FL_RW_MASK)) {
>               return -VTD_FR_WRITE;
>           }
> -        if (vtd_flpte_nonzero_rsvd(flpte, level)) {
> +        if (vtd_flpte_nonzero_rsvd(flpte, *flpte_level)) {
>               error_report_once("%s: detected flpte reserved non-zero "
>                                 "iova=0x%" PRIx64 ", level=0x%" PRIx32
>                                 "flpte=0x%" PRIx64 ", pasid=0x%" PRIX32 ")",
> -                              __func__, iova, level, flpte, pasid);
> +                              __func__, iova, *flpte_level, flpte, pasid);
>               return -VTD_FR_PAGING_ENTRY_RSVD;
>           }
>   
> @@ -2140,19 +2140,18 @@ static int vtd_iova_to_flpte(IntelIOMMUState *s, VTDContextEntry *ce,
>               return -VTD_FR_FS_BIT_UPDATE_FAILED;
>           }
>   
> -        if (vtd_is_last_pte(flpte, level)) {
> +        if (vtd_is_last_pte(flpte, *flpte_level)) {
>               if (is_write &&
>                   (vtd_set_flag_in_pte(addr, offset, flpte, VTD_FL_D) !=
>                                                                       
> MEMTX_OK)) {
>                       return -VTD_FR_FS_BIT_UPDATE_FAILED;
>               }
>               *flptep = flpte;
> -            *flpte_level = level;
>               return 0;
>           }
>   
>           addr = vtd_get_pte_addr(flpte, aw_bits);
> -        level--;
> +        (*flpte_level)--;
>       }
>   }
>   

--
Regards,
Yi Liu