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Re: [PATCH ats_vtd v5 04/22] intel_iommu: do not consider wait_desc as a
From: |
CLEMENT MATHIEU--DRIF |
Subject: |
Re: [PATCH ats_vtd v5 04/22] intel_iommu: do not consider wait_desc as an invalid descriptor |
Date: |
Thu, 4 Jul 2024 04:23:57 +0000 |
On 03/07/2024 09:29, Yi Liu wrote:
> Caution: External email. Do not open attachments or click links,
> unless this email comes from a known sender and you know the content
> is safe.
>
>
> On 2024/7/2 23:29, CLEMENT MATHIEU--DRIF wrote:
>>
>> On 02/07/2024 15:33, Yi Liu wrote:
>>> Caution: External email. Do not open attachments or click links,
>>> unless this email comes from a known sender and you know the content
>>> is safe.
>>>
>>>
>>> On 2024/7/2 13:52, CLEMENT MATHIEU--DRIF wrote:
>>>> From: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
>>>>
>>>> Signed-off-by: Clément Mathieu--Drif
>>>> <clement.mathieu--drif@eviden.com>
>>>> Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
>>>> ---
>>>> hw/i386/intel_iommu.c | 5 +++++
>>>> 1 file changed, 5 insertions(+)
>>>>
>>>> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
>>>> index 98996ededc..71cebe2fd3 100644
>>>> --- a/hw/i386/intel_iommu.c
>>>> +++ b/hw/i386/intel_iommu.c
>>>> @@ -3500,6 +3500,11 @@ static bool
>>>> vtd_process_wait_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc)
>>>> } else if (inv_desc->lo & VTD_INV_DESC_WAIT_IF) {
>>>> /* Interrupt flag */
>>>> vtd_generate_completion_event(s);
>>>> + } else if (inv_desc->lo & VTD_INV_DESC_WAIT_FN) {
>>>> + /*
>>>> + * SW = 0, IF = 0, FN = 1
>>>> + * Nothing to do as we process the events sequentially
>>>> + */
>>>
>>> This code looks a bit weird. SW field does not co-exist with IF. But
>>> either
>>> SW or IF can co-exist with FN flag. Is it? Have you already seen a wait
>>> descriptor that only has FN flag set but no SW nor IF flag?
>> Yes, my test suite triggers that condition
>
> I see. Spec indeed has such usage. Please add a comment for it.
> Since it does not need a response, so QEMU can just bypass it. Also
> please adjust the subject a bit. It's misleading. Perhaps
>
> "intel_iommu: Bypass barrier wait descriptor"
good idea, will do
>
> Spec CH 7.10
> a. Submit Invalidation Wait Descriptor (inv_wait_dsc) with Fence flag
> (FN=1) Set to Invalidation
> Queue. This ensures that all requests submitted to the Invalidation Queue
> ahead of this wait
> descriptor are processed and completed by remapping hardware before
> processing requests
> after the Invalidation Wait Descriptor. It is not required to specify SW
> flag (or IF flag) in this
> descriptor or for software to wait on its completion, as its function
> is to
> only act as a barrier.
>
>>>
>>>> } else {
>>>> error_report_once("%s: invalid wait desc: hi=%"PRIx64",
>>>> lo=%"PRIx64
>>>> " (unknown type)", __func__,
>>>> inv_desc->hi,
>>>
>>> --
>>> Regards,
>>> Yi Liu
>
> --
> Regards,
> Yi Liu
- [PATCH ats_vtd v5 03/22] intel_iommu: return page walk level even when the translation fails, (continued)
- [PATCH ats_vtd v5 08/22] intel_iommu: declare supported PASID size, CLEMENT MATHIEU--DRIF, 2024/07/02
- [PATCH ats_vtd v5 04/22] intel_iommu: do not consider wait_desc as an invalid descriptor, CLEMENT MATHIEU--DRIF, 2024/07/02
- Re: [PATCH ats_vtd v5 04/22] intel_iommu: do not consider wait_desc as an invalid descriptor, Yi Liu, 2024/07/02
- Re: [PATCH ats_vtd v5 04/22] intel_iommu: do not consider wait_desc as an invalid descriptor, CLEMENT MATHIEU--DRIF, 2024/07/02
- Re: [PATCH ats_vtd v5 04/22] intel_iommu: do not consider wait_desc as an invalid descriptor, cmd, 2024/07/02
- Re: [PATCH ats_vtd v5 04/22] intel_iommu: do not consider wait_desc as an invalid descriptor, Yi Liu, 2024/07/03
- Re: [PATCH ats_vtd v5 04/22] intel_iommu: do not consider wait_desc as an invalid descriptor, cmd, 2024/07/03
- Re: [PATCH ats_vtd v5 04/22] intel_iommu: do not consider wait_desc as an invalid descriptor,
CLEMENT MATHIEU--DRIF <=
[PATCH ats_vtd v5 13/22] intel_iommu: implement the get_address_space_pasid iommu operation, CLEMENT MATHIEU--DRIF, 2024/07/02
[PATCH ats_vtd v5 06/22] pcie: add helper to declare PASID capability for a pcie device, CLEMENT MATHIEU--DRIF, 2024/07/02
[PATCH ats_vtd v5 09/22] pci: cache the bus mastering status in the device, CLEMENT MATHIEU--DRIF, 2024/07/02
[PATCH ats_vtd v5 05/22] memory: add permissions in IOMMUAccessFlags, CLEMENT MATHIEU--DRIF, 2024/07/02
[PATCH ats_vtd v5 15/22] memory: Allow to store the PASID in IOMMUTLBEntry, CLEMENT MATHIEU--DRIF, 2024/07/02
[PATCH ats_vtd v5 16/22] intel_iommu: fill the PASID field when creating an instance of IOMMUTLBEntry, CLEMENT MATHIEU--DRIF, 2024/07/02
[PATCH ats_vtd v5 14/22] intel_iommu: implement the get_memory_region_pasid iommu operation, CLEMENT MATHIEU--DRIF, 2024/07/02
[PATCH ats_vtd v5 10/22] pci: add IOMMU operations to get address spaces and memory regions with PASID, CLEMENT MATHIEU--DRIF, 2024/07/02