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[PULL 04/30] disas/riscv: Support zcmop disassemble
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From: |
Alistair Francis |
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Subject: |
[PULL 04/30] disas/riscv: Support zcmop disassemble |
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Date: |
Thu, 18 Jul 2024 12:09:46 +1000 |
From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Although in QEMU disassemble, we usually lift compressed instruction
to an normal format when display the instruction name. For C.MOP.n,
it is more reasonable to directly display its compressed name, because
its behavior can be redefined by later extension.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Deepak Gupta <debug@rivosinc.com>
Message-ID: <20240709113652.1239-5-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
disas/riscv.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
index 0b82ab2322..d29cb1ff7d 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -946,6 +946,14 @@ typedef enum {
rv_mop_rr_5 = 915,
rv_mop_rr_6 = 916,
rv_mop_rr_7 = 917,
+ rv_c_mop_1 = 918,
+ rv_c_mop_3 = 919,
+ rv_c_mop_5 = 920,
+ rv_c_mop_7 = 921,
+ rv_c_mop_9 = 922,
+ rv_c_mop_11 = 923,
+ rv_c_mop_13 = 924,
+ rv_c_mop_15 = 925,
} rv_op;
/* register names */
@@ -2176,6 +2184,14 @@ const rv_opcode_data rvi_opcode_data[] = {
{ "mop.rr.5", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "mop.rr.6", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "mop.rr.7", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "c.mop.1", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
+ { "c.mop.3", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
+ { "c.mop.5", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
+ { "c.mop.7", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
+ { "c.mop.9", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
+ { "c.mop.11", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
+ { "c.mop.13", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
+ { "c.mop.15", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
};
/* CSR names */
@@ -2532,6 +2548,13 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa
isa)
break;
case 2: op = rv_op_c_li; break;
case 3:
+ if (dec->cfg->ext_zcmop) {
+ if ((((inst >> 2) & 0b111111) == 0b100000) &&
+ (((inst >> 11) & 0b11) == 0b0)) {
+ op = rv_c_mop_1 + ((inst >> 8) & 0b111);
+ break;
+ }
+ }
switch ((inst >> 7) & 0b11111) {
case 2: op = rv_op_c_addi16sp; break;
default: op = rv_op_c_lui; break;
--
2.45.2
- [PULL 00/30] riscv-to-apply queue, Alistair Francis, 2024/07/17
- [PULL 01/30] target/riscv: Add zimop extension, Alistair Francis, 2024/07/17
- [PULL 02/30] disas/riscv: Support zimop disassemble, Alistair Francis, 2024/07/17
- [PULL 03/30] target/riscv: Add zcmop extension, Alistair Francis, 2024/07/17
- [PULL 04/30] disas/riscv: Support zcmop disassemble,
Alistair Francis <=
- [PULL 05/30] target/riscv: Support Zama16b extension, Alistair Francis, 2024/07/17
- [PULL 07/30] target/riscv: Add AMO instructions for Zabha, Alistair Francis, 2024/07/17
- [PULL 09/30] target/riscv: Add amocas.[b|h] for Zabha, Alistair Francis, 2024/07/17
- [PULL 10/30] target/riscv: Expose zabha extension as a cpu property, Alistair Francis, 2024/07/17
- [PULL 08/30] target/riscv: Move gen_cmpxchg before adding amocas.[b|h], Alistair Francis, 2024/07/17
- [PULL 06/30] target/riscv: Move gen_amo before implement Zabha, Alistair Francis, 2024/07/17
- [PULL 11/30] disas/riscv: Support zabha disassemble, Alistair Francis, 2024/07/17
- [PULL 12/30] target/riscv: Validate the mode in write_vstvec, Alistair Francis, 2024/07/17