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[PULL 06/30] target/riscv: Move gen_amo before implement Zabha
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From: |
Alistair Francis |
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Subject: |
[PULL 06/30] target/riscv: Move gen_amo before implement Zabha |
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Date: |
Thu, 18 Jul 2024 12:09:48 +1000 |
From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240709113652.1239-7-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 21 +++++++++++++++++++++
target/riscv/insn_trans/trans_rva.c.inc | 21 ---------------------
2 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 8a546f4ece..133550d6e2 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1077,6 +1077,27 @@ static bool gen_unary_per_ol(DisasContext *ctx, arg_r2
*a, DisasExtend ext,
return gen_unary(ctx, a, ext, f_tl);
}
+static bool gen_amo(DisasContext *ctx, arg_atomic *a,
+ void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp),
+ MemOp mop)
+{
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ if (ctx->cfg_ptr->ext_zama16b) {
+ mop |= MO_ATOM_WITHIN16;
+ } else {
+ mop |= MO_ALIGN;
+ }
+
+ decode_save_opc(ctx);
+ src1 = get_address(ctx, a->rs1, 0);
+ func(dest, src1, src2, ctx->mem_idx, mop);
+
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
diff --git a/target/riscv/insn_trans/trans_rva.c.inc
b/target/riscv/insn_trans/trans_rva.c.inc
index eb080baddd..39bbf60f3c 100644
--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -96,27 +96,6 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp
mop)
return true;
}
-static bool gen_amo(DisasContext *ctx, arg_atomic *a,
- void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp),
- MemOp mop)
-{
- TCGv dest = dest_gpr(ctx, a->rd);
- TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE);
-
- if (ctx->cfg_ptr->ext_zama16b) {
- mop |= MO_ATOM_WITHIN16;
- } else {
- mop |= MO_ALIGN;
- }
-
- decode_save_opc(ctx);
- src1 = get_address(ctx, a->rs1, 0);
- func(dest, src1, src2, ctx->mem_idx, mop);
-
- gen_set_gpr(ctx, a->rd, dest);
- return true;
-}
-
static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a)
{
REQUIRE_A_OR_ZALRSC(ctx);
--
2.45.2
- [PULL 02/30] disas/riscv: Support zimop disassemble, (continued)
- [PULL 02/30] disas/riscv: Support zimop disassemble, Alistair Francis, 2024/07/17
- [PULL 03/30] target/riscv: Add zcmop extension, Alistair Francis, 2024/07/17
- [PULL 04/30] disas/riscv: Support zcmop disassemble, Alistair Francis, 2024/07/17
- [PULL 05/30] target/riscv: Support Zama16b extension, Alistair Francis, 2024/07/17
- [PULL 07/30] target/riscv: Add AMO instructions for Zabha, Alistair Francis, 2024/07/17
- [PULL 09/30] target/riscv: Add amocas.[b|h] for Zabha, Alistair Francis, 2024/07/17
- [PULL 10/30] target/riscv: Expose zabha extension as a cpu property, Alistair Francis, 2024/07/17
- [PULL 08/30] target/riscv: Move gen_cmpxchg before adding amocas.[b|h], Alistair Francis, 2024/07/17
- [PULL 06/30] target/riscv: Move gen_amo before implement Zabha,
Alistair Francis <=
- [PULL 11/30] disas/riscv: Support zabha disassemble, Alistair Francis, 2024/07/17
- [PULL 12/30] target/riscv: Validate the mode in write_vstvec, Alistair Francis, 2024/07/17
- [PULL 13/30] disas/riscv: Add decode for Zawrs extension, Alistair Francis, 2024/07/17
- [PULL 14/30] target/riscv/kvm: update KVM regs to Linux 6.10-rc5, Alistair Francis, 2024/07/17
- [PULL 15/30] target/riscv: Combine set_mode and set_virt functions., Alistair Francis, 2024/07/17
- [PULL 16/30] target/riscv: Fix the predicate functions for mhpmeventhX CSRs, Alistair Francis, 2024/07/17
- [PULL 17/30] target/riscv: Add cycle & instret privilege mode filtering properties, Alistair Francis, 2024/07/17
- [PULL 18/30] target/riscv: Add cycle & instret privilege mode filtering definitions, Alistair Francis, 2024/07/17
- [PULL 19/30] target/riscv: Add cycle & instret privilege mode filtering support, Alistair Francis, 2024/07/17
- [PULL 20/30] target/riscv: Only set INH fields if priv mode is available, Alistair Francis, 2024/07/17