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[PULL 07/30] target/riscv: Add AMO instructions for Zabha
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From: |
Alistair Francis |
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Subject: |
[PULL 07/30] target/riscv: Add AMO instructions for Zabha |
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Date: |
Thu, 18 Jul 2024 12:09:49 +1000 |
From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240709113652.1239-8-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_cfg.h | 1 +
target/riscv/insn32.decode | 20 +++
target/riscv/translate.c | 4 +-
target/riscv/insn_trans/trans_rvzabha.c.inc | 131 ++++++++++++++++++++
4 files changed, 155 insertions(+), 1 deletion(-)
create mode 100644 target/riscv/insn_trans/trans_rvzabha.c.inc
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index ddbfae37e5..120905a254 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -84,6 +84,7 @@ struct RISCVCPUConfig {
bool ext_zaamo;
bool ext_zacas;
bool ext_zama16b;
+ bool ext_zabha;
bool ext_zalrsc;
bool ext_zawrs;
bool ext_zfa;
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 60da673153..3bad6372f2 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -1021,3 +1021,23 @@ amocas_q 00101 . . ..... ..... 100 ..... 0101111
@atom_st
# *** Zimop may-be-operation extension ***
mop_r_n 1 . 00 .. 0111 .. ..... 100 ..... 1110011 @mop5
mop_rr_n 1 . 00 .. 1 ..... ..... 100 ..... 1110011 @mop3
+
+# *** Zabhb Standard Extension ***
+amoswap_b 00001 . . ..... ..... 000 ..... 0101111 @atom_st
+amoadd_b 00000 . . ..... ..... 000 ..... 0101111 @atom_st
+amoxor_b 00100 . . ..... ..... 000 ..... 0101111 @atom_st
+amoand_b 01100 . . ..... ..... 000 ..... 0101111 @atom_st
+amoor_b 01000 . . ..... ..... 000 ..... 0101111 @atom_st
+amomin_b 10000 . . ..... ..... 000 ..... 0101111 @atom_st
+amomax_b 10100 . . ..... ..... 000 ..... 0101111 @atom_st
+amominu_b 11000 . . ..... ..... 000 ..... 0101111 @atom_st
+amomaxu_b 11100 . . ..... ..... 000 ..... 0101111 @atom_st
+amoswap_h 00001 . . ..... ..... 001 ..... 0101111 @atom_st
+amoadd_h 00000 . . ..... ..... 001 ..... 0101111 @atom_st
+amoxor_h 00100 . . ..... ..... 001 ..... 0101111 @atom_st
+amoand_h 01100 . . ..... ..... 001 ..... 0101111 @atom_st
+amoor_h 01000 . . ..... ..... 001 ..... 0101111 @atom_st
+amomin_h 10000 . . ..... ..... 001 ..... 0101111 @atom_st
+amomax_h 10100 . . ..... ..... 001 ..... 0101111 @atom_st
+amominu_h 11000 . . ..... ..... 001 ..... 0101111 @atom_st
+amomaxu_h 11100 . . ..... ..... 001 ..... 0101111 @atom_st
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 133550d6e2..4a3e786560 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1083,8 +1083,9 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
{
TCGv dest = dest_gpr(ctx, a->rd);
TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+ MemOp size = mop & MO_SIZE;
- if (ctx->cfg_ptr->ext_zama16b) {
+ if (ctx->cfg_ptr->ext_zama16b && size >= MO_32) {
mop |= MO_ATOM_WITHIN16;
} else {
mop |= MO_ALIGN;
@@ -1118,6 +1119,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase,
target_ulong pc)
#include "insn_trans/trans_rvb.c.inc"
#include "insn_trans/trans_rvzicond.c.inc"
#include "insn_trans/trans_rvzacas.c.inc"
+#include "insn_trans/trans_rvzabha.c.inc"
#include "insn_trans/trans_rvzawrs.c.inc"
#include "insn_trans/trans_rvzicbo.c.inc"
#include "insn_trans/trans_rvzimop.c.inc"
diff --git a/target/riscv/insn_trans/trans_rvzabha.c.inc
b/target/riscv/insn_trans/trans_rvzabha.c.inc
new file mode 100644
index 0000000000..9093a1cfc1
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvzabha.c.inc
@@ -0,0 +1,131 @@
+/*
+ * RISC-V translation routines for the Zabha Standard Extension.
+ *
+ * Copyright (c) 2024 Alibaba Group
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_ZABHA(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zabha) { \
+ return false; \
+ } \
+} while (0)
+
+static bool trans_amoswap_b(DisasContext *ctx, arg_amoswap_b *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_SB);
+}
+
+static bool trans_amoadd_b(DisasContext *ctx, arg_amoadd_b *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_SB);
+}
+
+static bool trans_amoxor_b(DisasContext *ctx, arg_amoxor_b *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_SB);
+}
+
+static bool trans_amoand_b(DisasContext *ctx, arg_amoand_b *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_SB);
+}
+
+static bool trans_amoor_b(DisasContext *ctx, arg_amoor_b *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_SB);
+}
+
+static bool trans_amomin_b(DisasContext *ctx, arg_amomin_b *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_SB);
+}
+
+static bool trans_amomax_b(DisasContext *ctx, arg_amomax_b *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_SB);
+}
+
+static bool trans_amominu_b(DisasContext *ctx, arg_amominu_b *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_SB);
+}
+
+static bool trans_amomaxu_b(DisasContext *ctx, arg_amomaxu_b *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_SB);
+}
+
+static bool trans_amoswap_h(DisasContext *ctx, arg_amoswap_h *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_TESW);
+}
+
+static bool trans_amoadd_h(DisasContext *ctx, arg_amoadd_h *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_TESW);
+}
+
+static bool trans_amoxor_h(DisasContext *ctx, arg_amoxor_h *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_TESW);
+}
+
+static bool trans_amoand_h(DisasContext *ctx, arg_amoand_h *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_TESW);
+}
+
+static bool trans_amoor_h(DisasContext *ctx, arg_amoor_h *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_TESW);
+}
+
+static bool trans_amomin_h(DisasContext *ctx, arg_amomin_h *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_TESW);
+}
+
+static bool trans_amomax_h(DisasContext *ctx, arg_amomax_h *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_TESW);
+}
+
+static bool trans_amominu_h(DisasContext *ctx, arg_amominu_h *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_TESW);
+}
+
+static bool trans_amomaxu_h(DisasContext *ctx, arg_amomaxu_h *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_TESW);
+}
--
2.45.2
- [PULL 00/30] riscv-to-apply queue, Alistair Francis, 2024/07/17
- [PULL 01/30] target/riscv: Add zimop extension, Alistair Francis, 2024/07/17
- [PULL 02/30] disas/riscv: Support zimop disassemble, Alistair Francis, 2024/07/17
- [PULL 03/30] target/riscv: Add zcmop extension, Alistair Francis, 2024/07/17
- [PULL 04/30] disas/riscv: Support zcmop disassemble, Alistair Francis, 2024/07/17
- [PULL 05/30] target/riscv: Support Zama16b extension, Alistair Francis, 2024/07/17
- [PULL 07/30] target/riscv: Add AMO instructions for Zabha,
Alistair Francis <=
- [PULL 09/30] target/riscv: Add amocas.[b|h] for Zabha, Alistair Francis, 2024/07/17
- [PULL 10/30] target/riscv: Expose zabha extension as a cpu property, Alistair Francis, 2024/07/17
- [PULL 08/30] target/riscv: Move gen_cmpxchg before adding amocas.[b|h], Alistair Francis, 2024/07/17
- [PULL 06/30] target/riscv: Move gen_amo before implement Zabha, Alistair Francis, 2024/07/17
- [PULL 11/30] disas/riscv: Support zabha disassemble, Alistair Francis, 2024/07/17
- [PULL 12/30] target/riscv: Validate the mode in write_vstvec, Alistair Francis, 2024/07/17
- [PULL 13/30] disas/riscv: Add decode for Zawrs extension, Alistair Francis, 2024/07/17
- [PULL 14/30] target/riscv/kvm: update KVM regs to Linux 6.10-rc5, Alistair Francis, 2024/07/17
- [PULL 15/30] target/riscv: Combine set_mode and set_virt functions., Alistair Francis, 2024/07/17
- [PULL 16/30] target/riscv: Fix the predicate functions for mhpmeventhX CSRs, Alistair Francis, 2024/07/17