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[PULL 17/30] target/riscv: Add cycle & instret privilege mode filtering
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From: |
Alistair Francis |
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Subject: |
[PULL 17/30] target/riscv: Add cycle & instret privilege mode filtering properties |
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Date: |
Thu, 18 Jul 2024 12:09:59 +1000 |
From: Kaiwen Xue <kaiwenx@rivosinc.com>
This adds the properties for ISA extension smcntrpmf. Patches
implementing it will follow.
Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240711-smcntrpmf_v7-v8-3-b7c38ae7b263@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_cfg.h | 1 +
target/riscv/cpu.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 120905a254..8b272fb826 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -76,6 +76,7 @@ struct RISCVCPUConfig {
bool ext_ztso;
bool ext_smstateen;
bool ext_sstc;
+ bool ext_smcntrpmf;
bool ext_svadu;
bool ext_svinval;
bool ext_svnapot;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 33ef4eb795..4efe7ee3b0 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -182,6 +182,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
+ ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf),
ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
--
2.45.2
- [PULL 09/30] target/riscv: Add amocas.[b|h] for Zabha, (continued)
- [PULL 09/30] target/riscv: Add amocas.[b|h] for Zabha, Alistair Francis, 2024/07/17
- [PULL 10/30] target/riscv: Expose zabha extension as a cpu property, Alistair Francis, 2024/07/17
- [PULL 08/30] target/riscv: Move gen_cmpxchg before adding amocas.[b|h], Alistair Francis, 2024/07/17
- [PULL 06/30] target/riscv: Move gen_amo before implement Zabha, Alistair Francis, 2024/07/17
- [PULL 11/30] disas/riscv: Support zabha disassemble, Alistair Francis, 2024/07/17
- [PULL 12/30] target/riscv: Validate the mode in write_vstvec, Alistair Francis, 2024/07/17
- [PULL 13/30] disas/riscv: Add decode for Zawrs extension, Alistair Francis, 2024/07/17
- [PULL 14/30] target/riscv/kvm: update KVM regs to Linux 6.10-rc5, Alistair Francis, 2024/07/17
- [PULL 15/30] target/riscv: Combine set_mode and set_virt functions., Alistair Francis, 2024/07/17
- [PULL 16/30] target/riscv: Fix the predicate functions for mhpmeventhX CSRs, Alistair Francis, 2024/07/17
- [PULL 17/30] target/riscv: Add cycle & instret privilege mode filtering properties,
Alistair Francis <=
- [PULL 18/30] target/riscv: Add cycle & instret privilege mode filtering definitions, Alistair Francis, 2024/07/17
- [PULL 19/30] target/riscv: Add cycle & instret privilege mode filtering support, Alistair Francis, 2024/07/17
- [PULL 20/30] target/riscv: Only set INH fields if priv mode is available, Alistair Francis, 2024/07/17
- [PULL 21/30] target/riscv: Implement privilege mode filtering for cycle/instret, Alistair Francis, 2024/07/17
- [PULL 22/30] target/riscv: Save counter values during countinhibit update, Alistair Francis, 2024/07/17
- [PULL 23/30] target/riscv: Enforce WARL behavior for scounteren/hcounteren, Alistair Francis, 2024/07/17
- [PULL 25/30] target/riscv: More accurately model priv mode filtering., Alistair Francis, 2024/07/17
- [PULL 24/30] target/riscv: Start counters from both mhpmcounter and mcountinhibit, Alistair Francis, 2024/07/17