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[PULL 13/30] disas/riscv: Add decode for Zawrs extension
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From: |
Alistair Francis |
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Subject: |
[PULL 13/30] disas/riscv: Add decode for Zawrs extension |
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Date: |
Thu, 18 Jul 2024 12:09:55 +1000 |
From: Balaji Ravikumar <bravikumar@rivosinc.com>
Add disassembly support for these instructions from Zawrs:
* wrs.sto
* wrs.nto
Signed-off-by: Balaji Ravikumar <bravikumar@rivosinc.com>
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240705165316.127494-1-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
disas/riscv.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
index c8364c2b07..5965574d87 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -974,6 +974,8 @@ typedef enum {
rv_op_amomaxu_h = 943,
rv_op_amocas_b = 944,
rv_op_amocas_h = 945,
+ rv_op_wrs_sto = 946,
+ rv_op_wrs_nto = 947,
} rv_op;
/* register names */
@@ -2232,6 +2234,8 @@ const rv_opcode_data rvi_opcode_data[] = {
{ "amomaxu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
{ "amocas.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
{ "amocas.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+ { "wrs.sto", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
+ { "wrs.nto", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
};
/* CSR names */
@@ -3980,6 +3984,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 0: op = rv_op_ecall; break;
case 32: op = rv_op_ebreak; break;
case 64: op = rv_op_uret; break;
+ case 416: op = rv_op_wrs_nto; break;
+ case 928: op = rv_op_wrs_sto; break;
}
break;
case 256:
--
2.45.2
- [PULL 05/30] target/riscv: Support Zama16b extension, (continued)
- [PULL 05/30] target/riscv: Support Zama16b extension, Alistair Francis, 2024/07/17
- [PULL 07/30] target/riscv: Add AMO instructions for Zabha, Alistair Francis, 2024/07/17
- [PULL 09/30] target/riscv: Add amocas.[b|h] for Zabha, Alistair Francis, 2024/07/17
- [PULL 10/30] target/riscv: Expose zabha extension as a cpu property, Alistair Francis, 2024/07/17
- [PULL 08/30] target/riscv: Move gen_cmpxchg before adding amocas.[b|h], Alistair Francis, 2024/07/17
- [PULL 06/30] target/riscv: Move gen_amo before implement Zabha, Alistair Francis, 2024/07/17
- [PULL 11/30] disas/riscv: Support zabha disassemble, Alistair Francis, 2024/07/17
- [PULL 12/30] target/riscv: Validate the mode in write_vstvec, Alistair Francis, 2024/07/17
- [PULL 13/30] disas/riscv: Add decode for Zawrs extension,
Alistair Francis <=
- [PULL 14/30] target/riscv/kvm: update KVM regs to Linux 6.10-rc5, Alistair Francis, 2024/07/17
- [PULL 15/30] target/riscv: Combine set_mode and set_virt functions., Alistair Francis, 2024/07/17
- [PULL 16/30] target/riscv: Fix the predicate functions for mhpmeventhX CSRs, Alistair Francis, 2024/07/17
- [PULL 17/30] target/riscv: Add cycle & instret privilege mode filtering properties, Alistair Francis, 2024/07/17
- [PULL 18/30] target/riscv: Add cycle & instret privilege mode filtering definitions, Alistair Francis, 2024/07/17
- [PULL 19/30] target/riscv: Add cycle & instret privilege mode filtering support, Alistair Francis, 2024/07/17
- [PULL 20/30] target/riscv: Only set INH fields if priv mode is available, Alistair Francis, 2024/07/17
- [PULL 21/30] target/riscv: Implement privilege mode filtering for cycle/instret, Alistair Francis, 2024/07/17