Re: [PATCH] intel-iommu: fix Read DMAR IQA REG DW

[Yee Li]

> > When dmar_readq or devmem2 read the DW of IQA always 0UL because
> > "& VTD_IQA_QS". So, try to fix it.
> >
> > case:
> > after vtd_mem_write
> > IQA val: 0x100206801
> >
> > after vtd_mem_read
> > IQA val: 0x100206001
> >
> > Signed-off-by: yeeli <seven.yi.lee@gmail.com>
>
>
> how was this tested?

If VT-D hardware supports scalable mode, Linux will set the IQA DW (bit 11).
In qemu, the vtd_mem_write and vtd_update_iq_dw set DW well, however,
vtd_mem_read the DW wrong because "& VTD_IQA_QS" dropped the value
of DW (bit 11).

So testing the patch is easy,

config the "x-scalable-mode" option as below:

"-device intel-iommu,caching-mode=on,x-scalable-mode=on,aw-bits=48"

after Linux OS boot, check the IQA_REG DW (bit 11) as below:

IOMMU_DEBUGFS:

"cat /sys/kernel/debug/iommu/intel |grep IQA"
"IQA        0x90        0x00000001001da801"

or devmem2 read the reg:

"devmem2 0xfed90090"
"/dev/mem opened."
"Memory mapped at address 0x7f983014f000."
"Value at address 0xFED90090 (0x7f983014f000): 0x0"