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[PATCH v2 10/13] target/riscv: Enable sscofpmf for bare cpu by default
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From: |
Atish Patra |
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Subject: |
[PATCH v2 10/13] target/riscv: Enable sscofpmf for bare cpu by default |
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Date: |
Tue, 23 Jul 2024 16:30:07 -0700 |
Sscofpmf has been supported on virt machine for a long time. It is
required to enable profiling on virt machines. Let's enable it
by default for ease of usage.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1731dc461376..393d1d67120e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -494,6 +494,7 @@ static void rv64_base_cpu_init(Object *obj)
env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
+ cpu->cfg.ext_sscofpmf = true;
#endif
}
--
2.34.1
- [PATCH v2 00/13] Add RISC-V Counter delegation ISA extension support, Atish Patra, 2024/07/23
- [PATCH v2 01/13] target/riscv: Add properties for Indirect CSR Access extension, Atish Patra, 2024/07/23
- [PATCH v2 04/13] target/riscv: Support generic CSR indirect access, Atish Patra, 2024/07/23
- [PATCH v2 03/13] target/riscv: Enable S*stateen bits for AIA, Atish Patra, 2024/07/23
- [PATCH v2 02/13] target/riscv: Decouple AIA processing from xiselect and xireg, Atish Patra, 2024/07/23
- [PATCH v2 05/13] target/riscv: Add counter delegation definitions, Atish Patra, 2024/07/23
- [PATCH v2 07/13] target/riscv: Add counter delegation/configuration support, Atish Patra, 2024/07/23
- [PATCH v2 13/13] target/riscv: Enable PMU related extensions to preferred rule, Atish Patra, 2024/07/23
- [PATCH v2 10/13] target/riscv: Enable sscofpmf for bare cpu by default,
Atish Patra <=
- [PATCH v2 12/13] target/riscv: Add a preferred ISA extension rule, Atish Patra, 2024/07/23
- [PATCH v2 09/13] target/riscv: Invoke pmu init after feature enable, Atish Patra, 2024/07/23
- [PATCH v2 11/13] target/riscv: Repurpose the implied rule startergy, Atish Patra, 2024/07/23
- [PATCH v2 06/13] target/riscv: Add select value range check for counter delegation, Atish Patra, 2024/07/23
- [PATCH v2 08/13] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg, Atish Patra, 2024/07/23