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[PATCH v2 09/13] target/riscv: Invoke pmu init after feature enable
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From: |
Atish Patra |
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Subject: |
[PATCH v2 09/13] target/riscv: Invoke pmu init after feature enable |
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Date: |
Tue, 23 Jul 2024 16:30:06 -0700 |
The dependant ISA features are enabled at the end of cpu_realize
in finalize_features. Thus, PMU init should be invoked after that
only. Move the init invocation to riscv_tcg_cpu_finalize_features.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
target/riscv/tcg/tcg-cpu.c | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index b8814ab753bd..d78d5960cf30 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -898,6 +898,20 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error
**errp)
error_propagate(errp, local_err);
return;
}
+#ifndef CONFIG_USER_ONLY
+ if (cpu->cfg.pmu_mask) {
+ riscv_pmu_init(cpu, &local_err);
+ if (local_err != NULL) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ if (cpu->cfg.ext_sscofpmf) {
+ cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
+ riscv_pmu_timer_cb, cpu);
+ }
+ }
+#endif
}
void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
@@ -945,7 +959,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error
**errp)
#ifndef CONFIG_USER_ONLY
CPURISCVState *env = &cpu->env;
- Error *local_err = NULL;
tcg_cflags_set(CPU(cs), CF_PCREL);
@@ -953,19 +966,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error
**errp)
riscv_timer_init(cpu);
}
- if (cpu->cfg.pmu_mask) {
- riscv_pmu_init(cpu, &local_err);
- if (local_err != NULL) {
- error_propagate(errp, local_err);
- return false;
- }
-
- if (cpu->cfg.ext_sscofpmf) {
- cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
- riscv_pmu_timer_cb, cpu);
- }
- }
-
/* With H-Ext, VSSIP, VSTIP, VSEIP and SGEIP are hardwired to one. */
if (riscv_has_ext(env, RVH)) {
env->mideleg = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP;
--
2.34.1
- [PATCH v2 01/13] target/riscv: Add properties for Indirect CSR Access extension, (continued)
- [PATCH v2 01/13] target/riscv: Add properties for Indirect CSR Access extension, Atish Patra, 2024/07/23
- [PATCH v2 04/13] target/riscv: Support generic CSR indirect access, Atish Patra, 2024/07/23
- [PATCH v2 03/13] target/riscv: Enable S*stateen bits for AIA, Atish Patra, 2024/07/23
- [PATCH v2 02/13] target/riscv: Decouple AIA processing from xiselect and xireg, Atish Patra, 2024/07/23
- [PATCH v2 05/13] target/riscv: Add counter delegation definitions, Atish Patra, 2024/07/23
- [PATCH v2 07/13] target/riscv: Add counter delegation/configuration support, Atish Patra, 2024/07/23
- [PATCH v2 13/13] target/riscv: Enable PMU related extensions to preferred rule, Atish Patra, 2024/07/23
- [PATCH v2 10/13] target/riscv: Enable sscofpmf for bare cpu by default, Atish Patra, 2024/07/23
- [PATCH v2 12/13] target/riscv: Add a preferred ISA extension rule, Atish Patra, 2024/07/23
- [PATCH v2 09/13] target/riscv: Invoke pmu init after feature enable,
Atish Patra <=
- [PATCH v2 11/13] target/riscv: Repurpose the implied rule startergy, Atish Patra, 2024/07/23
- [PATCH v2 06/13] target/riscv: Add select value range check for counter delegation, Atish Patra, 2024/07/23
- [PATCH v2 08/13] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg, Atish Patra, 2024/07/23