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[PATCH v2 01/13] target/riscv: Add properties for Indirect CSR Access ex
From: |
Atish Patra |
Subject: |
[PATCH v2 01/13] target/riscv: Add properties for Indirect CSR Access extension |
Date: |
Tue, 23 Jul 2024 16:29:58 -0700 |
From: Kaiwen Xue <kaiwenx@rivosinc.com>
This adds the properties for sxcsrind. Definitions of new registers and
implementations will come with future patches.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu_cfg.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a90808a3bace..ebc19090b40d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -183,12 +183,14 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf),
+ ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_12_0, ext_smcsrind),
ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11),
ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),
+ ISA_EXT_DATA_ENTRY(sscsrind, PRIV_VERSION_1_12_0, ext_sscsrind),
ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12),
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 8b272fb826ef..b8a5174bc871 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -77,6 +77,8 @@ struct RISCVCPUConfig {
bool ext_smstateen;
bool ext_sstc;
bool ext_smcntrpmf;
+ bool ext_smcsrind;
+ bool ext_sscsrind;
bool ext_svadu;
bool ext_svinval;
bool ext_svnapot;
--
2.34.1
- [PATCH v2 00/13] Add RISC-V Counter delegation ISA extension support, Atish Patra, 2024/07/23
- [PATCH v2 01/13] target/riscv: Add properties for Indirect CSR Access extension,
Atish Patra <=
- [PATCH v2 04/13] target/riscv: Support generic CSR indirect access, Atish Patra, 2024/07/23
- [PATCH v2 03/13] target/riscv: Enable S*stateen bits for AIA, Atish Patra, 2024/07/23
- [PATCH v2 02/13] target/riscv: Decouple AIA processing from xiselect and xireg, Atish Patra, 2024/07/23
- [PATCH v2 05/13] target/riscv: Add counter delegation definitions, Atish Patra, 2024/07/23
- [PATCH v2 07/13] target/riscv: Add counter delegation/configuration support, Atish Patra, 2024/07/23
- [PATCH v2 13/13] target/riscv: Enable PMU related extensions to preferred rule, Atish Patra, 2024/07/23
- [PATCH v2 10/13] target/riscv: Enable sscofpmf for bare cpu by default, Atish Patra, 2024/07/23