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[PULL 32/96] ppc/pnv: Add big-core machine property
From: |
Nicholas Piggin |
Subject: |
[PULL 32/96] ppc/pnv: Add big-core machine property |
Date: |
Fri, 26 Jul 2024 09:53:05 +1000 |
Big-core implementation is complete, so expose it as a machine
property that may be set with big-core=on option on powernv9 and
powernv10 machines.
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/pnv.c | 61 ++++++++++++++++++++++++++++++++++++++--------------
1 file changed, 45 insertions(+), 16 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 4605a49d28..d19516c2d7 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -2581,6 +2581,34 @@ static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t
format,
return total_count;
}
+static bool pnv_machine_get_big_core(Object *obj, Error **errp)
+{
+ PnvMachineState *pnv = PNV_MACHINE(obj);
+ return pnv->big_core;
+}
+
+static void pnv_machine_set_big_core(Object *obj, bool value, Error **errp)
+{
+ PnvMachineState *pnv = PNV_MACHINE(obj);
+ pnv->big_core = value;
+}
+
+static bool pnv_machine_get_hb(Object *obj, Error **errp)
+{
+ PnvMachineState *pnv = PNV_MACHINE(obj);
+
+ return !!pnv->fw_load_addr;
+}
+
+static void pnv_machine_set_hb(Object *obj, bool value, Error **errp)
+{
+ PnvMachineState *pnv = PNV_MACHINE(obj);
+
+ if (value) {
+ pnv->fw_load_addr = 0x8000000;
+ }
+}
+
static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -2632,6 +2660,12 @@ static void pnv_machine_power9_class_init(ObjectClass
*oc, void *data)
pmc->dt_power_mgt = pnv_dt_power_mgt;
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
+
+ object_class_property_add_bool(oc, "big-core",
+ pnv_machine_get_big_core,
+ pnv_machine_set_big_core);
+ object_class_property_set_description(oc, "big-core",
+ "Use big-core (aka fused-core) mode");
}
static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data)
@@ -2668,6 +2702,17 @@ static void pnv_machine_power10_class_init(ObjectClass
*oc, void *data)
pnv_machine_p10_common_class_init(oc, data);
mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
+
+ /*
+ * This is the parent of POWER10 Rainier class, so properies go here
+ * rather than common init (which would add them to both parent and
+ * child which is invalid).
+ */
+ object_class_property_add_bool(oc, "big-core",
+ pnv_machine_get_big_core,
+ pnv_machine_set_big_core);
+ object_class_property_set_description(oc, "big-core",
+ "Use big-core (aka fused-core) mode");
}
static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data)
@@ -2680,22 +2725,6 @@ static void
pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data)
pmc->i2c_init = pnv_rainier_i2c_init;
}
-static bool pnv_machine_get_hb(Object *obj, Error **errp)
-{
- PnvMachineState *pnv = PNV_MACHINE(obj);
-
- return !!pnv->fw_load_addr;
-}
-
-static void pnv_machine_set_hb(Object *obj, bool value, Error **errp)
-{
- PnvMachineState *pnv = PNV_MACHINE(obj);
-
- if (value) {
- pnv->fw_load_addr = 0x8000000;
- }
-}
-
static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
{
CPUPPCState *env = cpu_env(cs);
--
2.45.2
- [PULL 22/96] ppc/pnv: use class attribute to limit SMT threads for different machines, (continued)
- [PULL 22/96] ppc/pnv: use class attribute to limit SMT threads for different machines, Nicholas Piggin, 2024/07/25
- [PULL 24/96] ppc: Add a core_index to CPUPPCState for SMT vCPUs, Nicholas Piggin, 2024/07/25
- [PULL 25/96] target/ppc: Add helpers to check for SMT sibling threads, Nicholas Piggin, 2024/07/25
- [PULL 23/96] ppc/pnv: Extend chip_pir class method to TIR as well, Nicholas Piggin, 2024/07/25
- [PULL 26/96] ppc: Add has_smt_siblings property to CPUPPCState, Nicholas Piggin, 2024/07/25
- [PULL 27/96] ppc/pnv: Add a big-core mode that joins two regular cores, Nicholas Piggin, 2024/07/25
- [PULL 28/96] ppc/pnv: Add allow for big-core differences in DT generation, Nicholas Piggin, 2024/07/25
- [PULL 29/96] ppc/pnv: Implement big-core PVR for Power9/10, Nicholas Piggin, 2024/07/25
- [PULL 30/96] ppc/pnv: Implement Power9 CPU core thread state indirect register, Nicholas Piggin, 2024/07/25
- [PULL 31/96] ppc/pnv: Add POWER10 ChipTOD quirk for big-core, Nicholas Piggin, 2024/07/25
- [PULL 32/96] ppc/pnv: Add big-core machine property,
Nicholas Piggin <=
- [PULL 33/96] ppc/pnv: Add a CPU nmi and resume function, Nicholas Piggin, 2024/07/25
- [PULL 36/96] ppc/pnv: Remove ppc target dependency from pnv_xscom.h, Nicholas Piggin, 2024/07/25
- [PULL 35/96] ppc/pnv: Add an LPAR per core machine option, Nicholas Piggin, 2024/07/25
- [PULL 34/96] ppc/pnv: Implement POWER10 PC xscom registers for direct controls, Nicholas Piggin, 2024/07/25
- [PULL 37/96] hw/ssi: Add SPI model, Nicholas Piggin, 2024/07/25
- [PULL 38/96] hw/ssi: Extend SPI model, Nicholas Piggin, 2024/07/25