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[PULL 33/96] ppc/pnv: Add a CPU nmi and resume function
From: |
Nicholas Piggin |
Subject: |
[PULL 33/96] ppc/pnv: Add a CPU nmi and resume function |
Date: |
Fri, 26 Jul 2024 09:53:06 +1000 |
Power CPUs have an execution control facility that can pause, resume,
and cause NMIs, among other things. Add a function that will nmi a CPU
and resume it if it was paused, in preparation for implementing the
control facility.
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/pnv.c | 14 +++++++++++++-
include/hw/ppc/pnv.h | 2 ++
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index d19516c2d7..084cfb9984 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -2751,11 +2751,23 @@ static void pnv_cpu_do_nmi_on_cpu(CPUState *cs,
run_on_cpu_data arg)
*/
env->spr[SPR_SRR1] |= SRR1_WAKESCOM;
}
+ if (arg.host_int == 1) {
+ cpu_resume(cs);
+ }
+}
+
+/*
+ * Send a SRESET (NMI) interrupt to the CPU, and resume execution if it was
+ * paused.
+ */
+void pnv_cpu_do_nmi_resume(CPUState *cs)
+{
+ async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_HOST_INT(1));
}
static void pnv_cpu_do_nmi(PnvChip *chip, PowerPCCPU *cpu, void *opaque)
{
- async_run_on_cpu(CPU(cpu), pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL);
+ async_run_on_cpu(CPU(cpu), pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_HOST_INT(0));
}
static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index c56d152889..b7858d310d 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -112,6 +112,8 @@ PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb);
#define PNV_FDT_ADDR 0x01000000
#define PNV_TIMEBASE_FREQ 512000000ULL
+void pnv_cpu_do_nmi_resume(CPUState *cs);
+
/*
* BMC helpers
*/
--
2.45.2
- [PULL 24/96] ppc: Add a core_index to CPUPPCState for SMT vCPUs, (continued)
- [PULL 24/96] ppc: Add a core_index to CPUPPCState for SMT vCPUs, Nicholas Piggin, 2024/07/25
- [PULL 25/96] target/ppc: Add helpers to check for SMT sibling threads, Nicholas Piggin, 2024/07/25
- [PULL 23/96] ppc/pnv: Extend chip_pir class method to TIR as well, Nicholas Piggin, 2024/07/25
- [PULL 26/96] ppc: Add has_smt_siblings property to CPUPPCState, Nicholas Piggin, 2024/07/25
- [PULL 27/96] ppc/pnv: Add a big-core mode that joins two regular cores, Nicholas Piggin, 2024/07/25
- [PULL 28/96] ppc/pnv: Add allow for big-core differences in DT generation, Nicholas Piggin, 2024/07/25
- [PULL 29/96] ppc/pnv: Implement big-core PVR for Power9/10, Nicholas Piggin, 2024/07/25
- [PULL 30/96] ppc/pnv: Implement Power9 CPU core thread state indirect register, Nicholas Piggin, 2024/07/25
- [PULL 31/96] ppc/pnv: Add POWER10 ChipTOD quirk for big-core, Nicholas Piggin, 2024/07/25
- [PULL 32/96] ppc/pnv: Add big-core machine property, Nicholas Piggin, 2024/07/25
- [PULL 33/96] ppc/pnv: Add a CPU nmi and resume function,
Nicholas Piggin <=
- [PULL 36/96] ppc/pnv: Remove ppc target dependency from pnv_xscom.h, Nicholas Piggin, 2024/07/25
- [PULL 35/96] ppc/pnv: Add an LPAR per core machine option, Nicholas Piggin, 2024/07/25
- [PULL 34/96] ppc/pnv: Implement POWER10 PC xscom registers for direct controls, Nicholas Piggin, 2024/07/25
- [PULL 37/96] hw/ssi: Add SPI model, Nicholas Piggin, 2024/07/25
- [PULL 38/96] hw/ssi: Extend SPI model, Nicholas Piggin, 2024/07/25