[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v6 17/20] tests/acpi: q35: Update host address width in DMAR
|
From: |
Jason Wang |
|
Subject: |
Re: [PATCH v6 17/20] tests/acpi: q35: Update host address width in DMAR |
|
Date: |
Fri, 13 Dec 2024 11:41:25 +0800 |
On Thu, Dec 12, 2024 at 4:42 PM Zhenzhong Duan <zhenzhong.duan@intel.com> wrote:
>
> Differences:
>
> @@ -1,39 +1,39 @@
> /*
> * Intel ACPI Component Architecture
> * AML/ASL+ Disassembler version 20200925 (64-bit version)
> * Copyright (c) 2000 - 2020 Intel Corporation
> *
> - * Disassembly of tests/data/acpi/x86/q35/DMAR.dmar, Mon Nov 11 15:31:18 2024
> + * Disassembly of /tmp/aml-SPJ4W2, Mon Nov 11 15:31:18 2024
> *
> * ACPI Data Table [DMAR]
> *
> * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
> */
>
> [000h 0000 4] Signature : "DMAR" [DMA Remapping
> table]
> [004h 0004 4] Table Length : 00000078
> [008h 0008 1] Revision : 01
> -[009h 0009 1] Checksum : 15
> +[009h 0009 1] Checksum : 0C
> [00Ah 0010 6] Oem ID : "BOCHS "
> [010h 0016 8] Oem Table ID : "BXPC "
> [018h 0024 4] Oem Revision : 00000001
> [01Ch 0028 4] Asl Compiler ID : "BXPC"
> [020h 0032 4] Asl Compiler Revision : 00000001
>
> -[024h 0036 1] Host Address Width : 26
> +[024h 0036 1] Host Address Width : 2F
> [025h 0037 1] Flags : 01
> [026h 0038 10] Reserved : 00 00 00 00 00 00 00 00 00 00
>
> [030h 0048 2] Subtable Type : 0000 [Hardware Unit
> Definition]
> [032h 0050 2] Length : 0040
>
> [034h 0052 1] Flags : 00
> [035h 0053 1] Reserved : 00
> [036h 0054 2] PCI Segment Number : 0000
> [038h 0056 8] Register Base Address : 00000000FED90000
>
> [040h 0064 1] Device Scope Type : 03 [IOAPIC Device]
> [041h 0065 1] Entry Length : 08
> [042h 0066 2] Reserved : 0000
> [044h 0068 1] Enumeration ID : 00
> [045h 0069 1] PCI Bus Number : FF
>
> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
> Acked-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Thanks
- [PATCH v6 09/20] intel_iommu: Set accessed and dirty bits during stage-1 translation, (continued)
- [PATCH v6 09/20] intel_iommu: Set accessed and dirty bits during stage-1 translation, Zhenzhong Duan, 2024/12/12
- [PATCH v6 08/20] intel_iommu: Check stage-1 translation result with interrupt range, Zhenzhong Duan, 2024/12/12
- [PATCH v6 10/20] intel_iommu: Flush stage-1 cache in iotlb invalidation, Zhenzhong Duan, 2024/12/12
- [PATCH v6 12/20] intel_iommu: Add an internal API to find an address space with PASID, Zhenzhong Duan, 2024/12/12
- [PATCH v6 14/20] intel_iommu: piotlb invalidation should notify unmap, Zhenzhong Duan, 2024/12/12
- [PATCH v6 11/20] intel_iommu: Process PASID-based iotlb invalidation, Zhenzhong Duan, 2024/12/12
- [PATCH v6 13/20] intel_iommu: Add support for PASID-based device IOTLB invalidation, Zhenzhong Duan, 2024/12/12
- [PATCH v6 16/20] intel_iommu: Set default aw_bits to 48 starting from QEMU 9.2, Zhenzhong Duan, 2024/12/12
- [PATCH v6 15/20] tests/acpi: q35: allow DMAR acpi table changes, Zhenzhong Duan, 2024/12/12
- [PATCH v6 17/20] tests/acpi: q35: Update host address width in DMAR, Zhenzhong Duan, 2024/12/12
- Re: [PATCH v6 17/20] tests/acpi: q35: Update host address width in DMAR,
Jason Wang <=
- [PATCH v6 18/20] intel_iommu: Introduce a property x-flts for stage-1 translation, Zhenzhong Duan, 2024/12/12
- [PATCH v6 19/20] intel_iommu: Introduce a property to control FS1GP cap bit setting, Zhenzhong Duan, 2024/12/12
- [PATCH v6 20/20] tests/qtest: Add intel-iommu test, Zhenzhong Duan, 2024/12/12
- Re: [PATCH v6 00/20] intel_iommu: Enable stage-1 translation for emulated device, CLEMENT MATHIEU--DRIF, 2024/12/12