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[PULL v2 24/39] hw/char/riscv_htif: Explicit little-endian implementatio
From: |
Alistair Francis |
Subject: |
[PULL v2 24/39] hw/char/riscv_htif: Explicit little-endian implementation |
Date: |
Fri, 20 Dec 2024 11:54:24 +1000 |
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Since our RISC-V system emulation is only built for little
endian, the HTIF device aims to interface with little endian
memory accesses, thus we can explicit htif_mm_ops:endianness
being DEVICE_LITTLE_ENDIAN.
In that case tswap64() is equivalent to le64_to_cpu(), as in
"convert this 64-bit little-endian value into host cpu order".
Replace to simplify.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241129154304.34946-3-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/char/riscv_htif.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
index 0345088e8b..3f84d8d673 100644
--- a/hw/char/riscv_htif.c
+++ b/hw/char/riscv_htif.c
@@ -29,7 +29,7 @@
#include "qemu/timer.h"
#include "qemu/error-report.h"
#include "exec/address-spaces.h"
-#include "exec/tswap.h"
+#include "qemu/bswap.h"
#include "sysemu/dma.h"
#include "sysemu/runstate.h"
@@ -212,11 +212,11 @@ static void htif_handle_tohost_write(HTIFState *s,
uint64_t val_written)
} else {
uint64_t syscall[8];
cpu_physical_memory_read(payload, syscall, sizeof(syscall));
- if (tswap64(syscall[0]) == PK_SYS_WRITE &&
- tswap64(syscall[1]) == HTIF_DEV_CONSOLE &&
- tswap64(syscall[3]) == HTIF_CONSOLE_CMD_PUTC) {
+ if (le64_to_cpu(syscall[0]) == PK_SYS_WRITE &&
+ le64_to_cpu(syscall[1]) == HTIF_DEV_CONSOLE &&
+ le64_to_cpu(syscall[3]) == HTIF_CONSOLE_CMD_PUTC) {
uint8_t ch;
- cpu_physical_memory_read(tswap64(syscall[2]), &ch, 1);
+ cpu_physical_memory_read(le64_to_cpu(syscall[2]), &ch, 1);
/*
* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks
@@ -324,6 +324,7 @@ static void htif_mm_write(void *opaque, hwaddr addr,
static const MemoryRegionOps htif_mm_ops = {
.read = htif_mm_read,
.write = htif_mm_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr,
--
2.47.1
- [PULL v2 11/39] hw/intc/riscv_aplic: rename is_kvm_aia(), (continued)
- [PULL v2 11/39] hw/intc/riscv_aplic: rename is_kvm_aia(), Alistair Francis, 2024/12/19
- [PULL v2 12/39] hw/riscv/virt.c: reduce virt_use_kvm_aia() usage, Alistair Francis, 2024/12/19
- [PULL v2 14/39] target/riscv/kvm: consider irqchip_split() in aia_create(), Alistair Francis, 2024/12/19
- [PULL v2 17/39] target/riscv/kvm: remove irqchip_split() restriction, Alistair Francis, 2024/12/19
- [PULL v2 16/39] hw/intc/riscv_aplic: add kvm_msicfgaddr for split mode aplic-imsic, Alistair Francis, 2024/12/19
- [PULL v2 18/39] docs: update riscv/virt.rst with kernel-irqchip=split support, Alistair Francis, 2024/12/19
- [PULL v2 19/39] hw/riscv: Add Microblaze V generic board, Alistair Francis, 2024/12/19
- [PULL v2 20/39] qtest: allow SPCR acpi table changes, Alistair Francis, 2024/12/19
- [PULL v2 21/39] hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format, Alistair Francis, 2024/12/19
- [PULL v2 22/39] tests/qtest/bios-tables-test: Update virt SPCR golden reference for RISC-V, Alistair Francis, 2024/12/19
- [PULL v2 24/39] hw/char/riscv_htif: Explicit little-endian implementation,
Alistair Francis <=
- [PULL v2 29/39] target/riscv: Add svukte extension capability variable, Alistair Francis, 2024/12/19
- [PULL v2 23/39] MAINTAINERS: Cover RISC-V HTIF interface, Alistair Francis, 2024/12/19
- [PULL v2 30/39] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled, Alistair Francis, 2024/12/19
- [PULL v2 28/39] hw/riscv: Add the checking if DTB overlaps to kernel or initrd, Alistair Francis, 2024/12/19
- [PULL v2 26/39] hw/riscv: Support to load DTB after 3GB memory on 64-bit system., Alistair Francis, 2024/12/19
- [PULL v2 27/39] hw/riscv: Add a new struct RISCVBootInfo, Alistair Francis, 2024/12/19
- [PULL v2 25/39] hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses, Alistair Francis, 2024/12/19
- [PULL v2 31/39] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled, Alistair Francis, 2024/12/19
- [PULL v2 32/39] target/riscv: Check memory access to meet svukte rule, Alistair Francis, 2024/12/19
- [PULL v2 34/39] target/riscv: Check svukte is not enabled in RV32, Alistair Francis, 2024/12/19