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[PULL v2 25/39] hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bi
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From: |
Alistair Francis |
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Subject: |
[PULL v2 25/39] hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses |
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Date: |
Fri, 20 Dec 2024 11:54:25 +1000 |
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Looking at htif_mm_ops[] read/write handlers, we notice they
expect 32-bit values to accumulate into to the 'fromhost' and
'tohost' 64-bit variables. Explicit by setting the .impl
min/max fields.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241129154304.34946-4-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/char/riscv_htif.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
index 3f84d8d673..db69b5e3ca 100644
--- a/hw/char/riscv_htif.c
+++ b/hw/char/riscv_htif.c
@@ -325,6 +325,10 @@ static const MemoryRegionOps htif_mm_ops = {
.read = htif_mm_read,
.write = htif_mm_write,
.endianness = DEVICE_LITTLE_ENDIAN,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr,
--
2.47.1
- [PULL v2 20/39] qtest: allow SPCR acpi table changes, (continued)
- [PULL v2 20/39] qtest: allow SPCR acpi table changes, Alistair Francis, 2024/12/19
- [PULL v2 21/39] hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format, Alistair Francis, 2024/12/19
- [PULL v2 22/39] tests/qtest/bios-tables-test: Update virt SPCR golden reference for RISC-V, Alistair Francis, 2024/12/19
- [PULL v2 24/39] hw/char/riscv_htif: Explicit little-endian implementation, Alistair Francis, 2024/12/19
- [PULL v2 29/39] target/riscv: Add svukte extension capability variable, Alistair Francis, 2024/12/19
- [PULL v2 23/39] MAINTAINERS: Cover RISC-V HTIF interface, Alistair Francis, 2024/12/19
- [PULL v2 30/39] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled, Alistair Francis, 2024/12/19
- [PULL v2 28/39] hw/riscv: Add the checking if DTB overlaps to kernel or initrd, Alistair Francis, 2024/12/19
- [PULL v2 26/39] hw/riscv: Support to load DTB after 3GB memory on 64-bit system., Alistair Francis, 2024/12/19
- [PULL v2 27/39] hw/riscv: Add a new struct RISCVBootInfo, Alistair Francis, 2024/12/19
- [PULL v2 25/39] hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses,
Alistair Francis <=
- [PULL v2 31/39] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled, Alistair Francis, 2024/12/19
- [PULL v2 32/39] target/riscv: Check memory access to meet svukte rule, Alistair Francis, 2024/12/19
- [PULL v2 34/39] target/riscv: Check svukte is not enabled in RV32, Alistair Francis, 2024/12/19
- [PULL v2 33/39] target/riscv: Expose svukte ISA extension, Alistair Francis, 2024/12/19
- [PULL v2 35/39] target/riscv: Include missing headers in 'vector_internals.h', Alistair Francis, 2024/12/19
- [PULL v2 37/39] target/riscv/tcg: hide warn for named feats when disabling via priv_ver, Alistair Francis, 2024/12/19
- [PULL v2 36/39] target/riscv: Include missing headers in 'internals.h', Alistair Francis, 2024/12/19
- [PULL v2 39/39] target/riscv: add support for RV64 Xiangshan Nanhu CPU, Alistair Francis, 2024/12/19
- [PULL v2 38/39] target/riscv: add ssstateen, Alistair Francis, 2024/12/19
- Re: [PULL v2 00/39] riscv-to-apply queue, Stefan Hajnoczi, 2024/12/21