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[Qemu-riscv] [PATCH v1 09/23] riscv: tcg-target: Add the instruction emi
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From: |
Alistair Francis |
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Subject: |
[Qemu-riscv] [PATCH v1 09/23] riscv: tcg-target: Add the instruction emitters |
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Date: |
Wed, 12 Dec 2018 19:44:14 +0000 |
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
tcg/riscv/tcg-target.inc.c | 48 ++++++++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 08838027cd..d198cfd5f7 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -374,3 +374,51 @@ static int32_t encode_uj(RISCVInsn opc, TCGReg rd,
uint32_t imm)
{
return opc | (rd & 0x1f) << 7 | encode_ujimm20(imm);
}
+
+/*
+ * RISC-V instruction emitters
+ */
+
+static void tcg_out_opc_reg(TCGContext *s, RISCVInsn opc,
+ TCGReg rd, TCGReg rs1, TCGReg rs2)
+{
+ tcg_out32(s, encode_r(opc, rd, rs1, rs2));
+}
+
+static void tcg_out_opc_imm(TCGContext *s, RISCVInsn opc,
+ TCGReg rd, TCGReg rs1, TCGArg imm)
+{
+ tcg_out32(s, encode_i(opc, rd, rs1, imm));
+}
+
+static void tcg_out_opc_store(TCGContext *s, RISCVInsn opc,
+ TCGReg rs1, TCGReg rs2, uint32_t imm)
+{
+ tcg_out32(s, encode_s(opc, rs1, rs2, imm));
+}
+
+static void tcg_out_opc_branch(TCGContext *s, RISCVInsn opc,
+ TCGReg rs1, TCGReg rs2, uint32_t imm)
+{
+ tcg_out32(s, encode_sb(opc, rs1, rs2, imm));
+}
+
+static void tcg_out_opc_upper(TCGContext *s, RISCVInsn opc,
+ TCGReg rd, uint32_t imm)
+{
+ tcg_out32(s, encode_u(opc, rd, imm));
+}
+
+static void tcg_out_opc_jump(TCGContext *s, RISCVInsn opc,
+ TCGReg rd, uint32_t imm)
+{
+ tcg_out32(s, encode_uj(opc, rd, imm));
+}
+
+static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
+{
+ int i;
+ for (i = 0; i < count; ++i) {
+ p[i] = encode_i(OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0);
+ }
+}
--
2.19.1
- [Qemu-riscv] [PATCH v1 00/23] Add RISC-V TCG backend support, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 01/23] elf.h: Add the RISCV ELF magic numbers, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 02/23] linux-user: Add host dependency for RISC-V 32-bit, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 03/23] linux-user: Add host dependency for RISC-V 64-bit, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 04/23] exec: Add RISC-V GCC poison macro, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 05/23] riscv: Add the tcg-target header file, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 06/23] riscv: Add the tcg target registers, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 08/23] riscv: tcg-target: Add the immediate encoders, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 07/23] riscv: tcg-target: Add support for the constraints, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 09/23] riscv: tcg-target: Add the instruction emitters,
Alistair Francis <=
- [Qemu-riscv] [PATCH v1 10/23] riscv: tcg-target: Add the relocation functions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 11/23] riscv: tcg-target: Add the mov and movi instruction, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 12/23] riscv: tcg-target: Add the extract instructions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 13/23] riscv: tcg-target: Add the out load and store instructions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 14/23] riscv: tcg-target: Add the add2 and sub2 instructions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 15/23] riscv: tcg-target: Add branch and jump instructions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 16/23] riscv: tcg-target: Add slowpath load and store instructions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 17/23] riscv: tcg-target: Add direct load and store instructions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 18/23] riscv: tcg-target: Add the out op decoder, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 19/23] riscv: tcg-target: Add the prologue generation and register the JIT, Alistair Francis, 2018/12/12