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[Qemu-riscv] [PATCH v1 13/23] riscv: tcg-target: Add the out load and st
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From: |
Alistair Francis |
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Subject: |
[Qemu-riscv] [PATCH v1 13/23] riscv: tcg-target: Add the out load and store instructions |
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Date: |
Wed, 12 Dec 2018 19:44:51 +0000 |
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
tcg/riscv/tcg-target.inc.c | 65 ++++++++++++++++++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 6d63541da0..57084e747b 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -616,3 +616,68 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg ret,
TCGReg arg)
{
tcg_out_opc_imm(s, OPC_ADDIW, ret, arg, 0);
}
+
+static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data,
+ TCGReg addr, intptr_t offset)
+{
+ intptr_t imm12 = sextreg(offset, 0, 12);
+
+ if (offset != imm12) {
+ intptr_t diff = offset - (uintptr_t)s->code_ptr;
+
+ if (addr == TCG_REG_ZERO && diff == (int32_t)diff) {
+ imm12 = sextreg(diff, 0, 12);
+ tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP2, diff - imm12);
+ } else {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12);
+ if (addr != TCG_REG_ZERO) {
+ tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, addr);
+ }
+ }
+ addr = TCG_REG_TMP2;
+ }
+
+ switch (opc) {
+ case OPC_SB:
+ case OPC_SH:
+ case OPC_SW:
+ case OPC_SD:
+ tcg_out_opc_store(s, opc, addr, data, imm12);
+ break;
+ case OPC_LB:
+ case OPC_LBU:
+ case OPC_LH:
+ case OPC_LHU:
+ case OPC_LW:
+ case OPC_LWU:
+ case OPC_LD:
+ tcg_out_opc_imm(s, opc, data, addr, imm12);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
+ TCGReg arg1, intptr_t arg2)
+{
+ bool is32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32);
+ tcg_out_ldst(s, is32bit ? OPC_LW : OPC_LD, arg, arg1, arg2);
+}
+
+static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
+ TCGReg arg1, intptr_t arg2)
+{
+ bool is32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32);
+ tcg_out_ldst(s, is32bit ? OPC_SW : OPC_SD, arg, arg1, arg2);
+}
+
+static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
+ TCGReg base, intptr_t ofs)
+{
+ if (val == 0) {
+ tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
+ return true;
+ }
+ return false;
+}
--
2.19.1
- [Qemu-riscv] [PATCH v1 04/23] exec: Add RISC-V GCC poison macro, (continued)
- [Qemu-riscv] [PATCH v1 04/23] exec: Add RISC-V GCC poison macro, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 05/23] riscv: Add the tcg-target header file, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 06/23] riscv: Add the tcg target registers, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 08/23] riscv: tcg-target: Add the immediate encoders, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 07/23] riscv: tcg-target: Add support for the constraints, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 09/23] riscv: tcg-target: Add the instruction emitters, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 10/23] riscv: tcg-target: Add the relocation functions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 11/23] riscv: tcg-target: Add the mov and movi instruction, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 12/23] riscv: tcg-target: Add the extract instructions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 13/23] riscv: tcg-target: Add the out load and store instructions,
Alistair Francis <=
- [Qemu-riscv] [PATCH v1 14/23] riscv: tcg-target: Add the add2 and sub2 instructions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 15/23] riscv: tcg-target: Add branch and jump instructions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 16/23] riscv: tcg-target: Add slowpath load and store instructions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 17/23] riscv: tcg-target: Add direct load and store instructions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 18/23] riscv: tcg-target: Add the out op decoder, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 19/23] riscv: tcg-target: Add the prologue generation and register the JIT, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 20/23] riscv: tcg-target: Add the target init code, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 21/23] tcg: Add RISC-V cpu signal handler, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 22/23] dias: Add RISC-V support, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 23/23] configure: Add support for building RISC-V host, Alistair Francis, 2018/12/12