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[Qemu-riscv] [PATCH v1 15/23] riscv: tcg-target: Add branch and jump ins
From: |
Alistair Francis |
Subject: |
[Qemu-riscv] [PATCH v1 15/23] riscv: tcg-target: Add branch and jump instructions |
Date: |
Wed, 12 Dec 2018 19:45:10 +0000 |
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/riscv/tcg-target.inc.c | 142 +++++++++++++++++++++++++++++++++++++
1 file changed, 142 insertions(+)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 586a8917c7..f1ebd86516 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -736,3 +736,145 @@ static void tcg_out_addsub2(TCGContext *s,
tcg_out_opc_reg(s, opc_add, rh, th, TCG_REG_TMP0);
}
}
+
+static const struct {
+ RISCVInsn op;
+ bool swap;
+} tcg_brcond_to_riscv[] = {
+ [TCG_COND_EQ] = { OPC_BEQ, false },
+ [TCG_COND_NE] = { OPC_BNE, false },
+ [TCG_COND_LT] = { OPC_BLT, false },
+ [TCG_COND_GE] = { OPC_BGE, false },
+ [TCG_COND_LE] = { OPC_BGE, true },
+ [TCG_COND_GT] = { OPC_BLT, true },
+ [TCG_COND_LTU] = { OPC_BLTU, false },
+ [TCG_COND_GEU] = { OPC_BGEU, false },
+ [TCG_COND_LEU] = { OPC_BGEU, true },
+ [TCG_COND_GTU] = { OPC_BLTU, true }
+};
+
+static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
+ TCGReg arg2, TCGLabel *l)
+{
+ RISCVInsn op = tcg_brcond_to_riscv[cond].op;
+
+ tcg_debug_assert(op != 0);
+
+ if (tcg_brcond_to_riscv[cond].swap) {
+ TCGReg t = arg1;
+ arg1 = arg2;
+ arg2 = t;
+ }
+
+ if (l->has_value) {
+ intptr_t diff = tcg_pcrel_diff(s, l->u.value_ptr);
+ if (diff == sextreg(diff, 0, 12)) {
+ tcg_out_opc_branch(s, op, arg1, arg2, diff);
+ } else {
+ /* Invert the conditional branch. */
+ tcg_out_opc_branch(s, op ^ (1 << 12), arg1, arg2, 8);
+ tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, diff - 4);
+ }
+ } else {
+ tcg_out_reloc(s, s->code_ptr, R_RISCV_BRANCH, l, 0);
+ tcg_out_opc_branch(s, op, arg1, arg2, 0);
+ /* NOP to allow patching later */
+ tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0);
+ }
+}
+
+static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
+ TCGReg arg1, TCGReg arg2)
+{
+ switch (cond) {
+ case TCG_COND_EQ:
+ tcg_out_opc_reg(s, OPC_SUB, ret, arg1, arg2);
+ tcg_out_opc_imm(s, OPC_SLTIU, ret, ret, 1);
+ break;
+ case TCG_COND_NE:
+ tcg_out_opc_reg(s, OPC_SUB, ret, arg1, arg2);
+ tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, ret);
+ break;
+ case TCG_COND_LT:
+ tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2);
+ break;
+ case TCG_COND_GE:
+ tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2);
+ tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
+ break;
+ case TCG_COND_LE:
+ tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1);
+ tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
+ break;
+ case TCG_COND_GT:
+ tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1);
+ break;
+ case TCG_COND_LTU:
+ tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2);
+ break;
+ case TCG_COND_GEU:
+ tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2);
+ tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
+ break;
+ case TCG_COND_LEU:
+ tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1);
+ tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
+ break;
+ case TCG_COND_GTU:
+ tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1);
+ break;
+ default:
+ g_assert_not_reached();
+ break;
+ }
+}
+
+static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah,
+ TCGReg bl, TCGReg bh, TCGLabel *l)
+{
+ /* todo */
+ g_assert_not_reached();
+}
+
+static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
+ TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh)
+{
+ /* todo */
+ g_assert_not_reached();
+}
+
+static inline void tcg_out_goto(TCGContext *s, tcg_insn_unit *target)
+{
+ ptrdiff_t offset = tcg_pcrel_diff(s, target);
+ tcg_debug_assert(offset == sextreg(offset, 1, 20) << 1);
+ tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, offset);
+}
+
+static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail)
+{
+ TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA;
+ ptrdiff_t offset = tcg_pcrel_diff(s, arg);
+ if (offset == sextreg(offset, 1, 20) << 1) {
+ /* short jump: -2097150 to 2097152 */
+ tcg_out_opc_jump(s, OPC_JAL, link, offset);
+ } else if (TCG_TARGET_REG_BITS == 32 ||
+ offset == sextreg(offset, 1, 31) << 1) {
+ /* long jump: -2147483646 to 2147483648 */
+ tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP0, 0);
+ tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0);
+ reloc_call(s->code_ptr - 2, arg);
+ } else if (TCG_TARGET_REG_BITS == 64) {
+ /* far jump: 64-bit */
+ tcg_target_long imm = sextreg((tcg_target_long)arg, 0, 12);
+ tcg_target_long base = (tcg_target_long)arg - imm;
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, base);
+ tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm);
+ } else {
+ g_assert_not_reached();
+ }
+}
+
+static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg)
+{
+ tcg_out_call_int(s, arg, false);
+}
--
2.19.1
- Re: [Qemu-riscv] [PATCH v1 05/23] riscv: Add the tcg-target header file, (continued)
- [Qemu-riscv] [PATCH v1 06/23] riscv: Add the tcg target registers, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 08/23] riscv: tcg-target: Add the immediate encoders, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 07/23] riscv: tcg-target: Add support for the constraints, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 09/23] riscv: tcg-target: Add the instruction emitters, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 10/23] riscv: tcg-target: Add the relocation functions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 11/23] riscv: tcg-target: Add the mov and movi instruction, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 12/23] riscv: tcg-target: Add the extract instructions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 13/23] riscv: tcg-target: Add the out load and store instructions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 14/23] riscv: tcg-target: Add the add2 and sub2 instructions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 15/23] riscv: tcg-target: Add branch and jump instructions,
Alistair Francis <=
- [Qemu-riscv] [PATCH v1 16/23] riscv: tcg-target: Add slowpath load and store instructions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 17/23] riscv: tcg-target: Add direct load and store instructions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 18/23] riscv: tcg-target: Add the out op decoder, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 19/23] riscv: tcg-target: Add the prologue generation and register the JIT, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 20/23] riscv: tcg-target: Add the target init code, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 21/23] tcg: Add RISC-V cpu signal handler, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 22/23] dias: Add RISC-V support, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 23/23] configure: Add support for building RISC-V host, Alistair Francis, 2018/12/12
- Re: [Qemu-riscv] [PATCH v1 00/23] Add RISC-V TCG backend support, Richard Henderson, 2018/12/12