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[Qemu-riscv] [PULL 04/32] target/riscv: Implement riscv_cpu_unassigned_a
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 04/32] target/riscv: Implement riscv_cpu_unassigned_access |
Date: |
Wed, 3 Jul 2019 01:40:20 -0700 |
From: Michael Clark <address@hidden>
This patch adds support for the riscv_cpu_unassigned_access call
and will raise a load or store access fault.
Signed-off-by: Michael Clark <address@hidden>
[Changes by AF:
- Squash two patches and rewrite commit message
- Set baddr to the access address
]
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 2 ++
target/riscv/cpu_helper.c | 16 ++++++++++++++++
3 files changed, 19 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0632ac08cf35..5b9fae608cca 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -482,6 +482,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
+ cc->do_unassigned_access = riscv_cpu_unassigned_access;
cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
#endif
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index b47cde501766..2e743312536b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -259,6 +259,8 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr
addr,
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
+void riscv_cpu_unassigned_access(CPUState *cpu, hwaddr addr, bool is_write,
+ bool is_exec, int unused, unsigned size);
char *riscv_isa_string(RISCVCPU *cpu);
void riscv_cpu_list(void);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 8b6754b91798..0bbfb7f48b79 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -375,6 +375,22 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr
addr)
return phys_addr;
}
+void riscv_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write,
+ bool is_exec, int unused, unsigned size)
+{
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+
+ if (is_write) {
+ cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
+ } else {
+ cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
+ }
+
+ env->badaddr = addr;
+ riscv_raise_exception(&cpu->env, cs->exception_index, GETPC());
+}
+
void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type, int mmu_idx,
uintptr_t retaddr)
--
2.21.0
- [Qemu-riscv] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 01/32] target/riscv: Allow setting ISA extensions via CPU props, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 03/32] target/riscv: Fix PMP range boundary address bug, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 02/32] sifive_prci: Read and write PRCI registers, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 05/32] RISC-V: Only Check PMP if MMU translation succeeds, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 04/32] target/riscv: Implement riscv_cpu_unassigned_access,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 06/32] RISC-V: Raise access fault exceptions on PMP violations, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 07/32] RISC-V: Check for the effective memory privilege mode during PMP checks, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 08/32] RISC-V: Check PMP during Page Table Walks, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 09/32] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 10/32] RISC-V: Fix a PMP check with the correct access size, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 11/32] riscv: virt: Correct pci "bus-range" encoding, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 12/32] RISC-V: Fix a memory leak when realizing a sifive_e, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 13/32] target/riscv: Restructure deprecatd CPUs, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 14/32] target/riscv: Add the privledge spec version 1.11.0, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 17/32] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1, Palmer Dabbelt, 2019/07/03