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[Qemu-riscv] [PULL 17/32] qemu-deprecated.texi: Deprecate the RISC-V pri
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From: |
Palmer Dabbelt |
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Subject: |
[Qemu-riscv] [PULL 17/32] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1 |
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Date: |
Wed, 3 Jul 2019 01:40:33 -0700 |
From: Alistair Francis <address@hidden>
Deprecate the RISC-V privledge spec version 1.09.1 in favour of the new
1.10.0 and the ratified 1.11.0.
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
qemu-deprecated.texi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/qemu-deprecated.texi b/qemu-deprecated.texi
index df04f2840bd9..97ea4ef3001a 100644
--- a/qemu-deprecated.texi
+++ b/qemu-deprecated.texi
@@ -144,6 +144,14 @@ The ``acl_show'', ``acl_reset'', ``acl_policy'',
``acl_add'', and
``acl_remove'' commands are deprecated with no replacement. Authorization
for VNC should be performed using the pluggable QAuthZ objects.
+@section Guest Emulator ISAs
+
+@subsection RISC-V ISA privledge specification version 1.09.1 (since 4.1)
+
+The RISC-V ISA privledge specification version 1.09.1 has been deprecated.
+QEMU supports both the newer version 1.10.0 and the ratified version 1.11.0,
these
+should be used instead of the 1.09.1 version.
+
@section System emulator CPUS
@subsection RISC-V ISA CPUs (since 4.1)
--
2.21.0
- [Qemu-riscv] [PULL 04/32] target/riscv: Implement riscv_cpu_unassigned_access, (continued)
- [Qemu-riscv] [PULL 04/32] target/riscv: Implement riscv_cpu_unassigned_access, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 06/32] RISC-V: Raise access fault exceptions on PMP violations, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 07/32] RISC-V: Check for the effective memory privilege mode during PMP checks, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 08/32] RISC-V: Check PMP during Page Table Walks, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 09/32] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 10/32] RISC-V: Fix a PMP check with the correct access size, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 11/32] riscv: virt: Correct pci "bus-range" encoding, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 12/32] RISC-V: Fix a memory leak when realizing a sifive_e, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 13/32] target/riscv: Restructure deprecatd CPUs, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 14/32] target/riscv: Add the privledge spec version 1.11.0, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 17/32] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 15/32] target/riscv: Add the mcountinhibit CSR, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 16/32] target/riscv: Set privledge spec 1.11.0 as default, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 18/32] target/riscv: Require either I or E base extension, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 20/32] target/riscv: Add support for disabling/enabling Counters, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 24/32] RISC-V: Update syscall list for 32-bit support., Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 19/32] target/riscv: Remove user version information, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 21/32] RISC-V: Add support for the Zifencei extension, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 23/32] RISC-V: Clear load reservations on context switch and SC, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 28/32] riscv: sifive_u: Do not create hard-coded phandles in DT, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 32/32] hw/riscv: Extend the kernel loading support, Palmer Dabbelt, 2019/07/03