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[Qemu-riscv] [PULL 09/32] RISC-V: Fix a PMP bug where it succeeds even i
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 09/32] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off |
Date: |
Wed, 3 Jul 2019 01:40:25 -0700 |
From: Hesham Almatary <address@hidden>
The current implementation returns 1 (PMP check success) if the address is in
range even if the PMP entry is off. This is a bug.
For example, if there is a PMP check in S-Mode which is in range, but its PMP
entry is off, this will succeed, which it should not.
The patch fixes this bug by only checking the PMP permissions if the address is
in range and its corresponding PMP entry it not off. Otherwise, it will keep
the ret = -1 which will be checked and handled correctly at the end of the
function.
Signed-off-by: Hesham Almatary <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/pmp.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 5944f4cb6607..958c7502a0e0 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -258,11 +258,12 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong
addr,
/* fully inside */
const uint8_t a_field =
pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg);
- if ((s + e) == 2) {
- if (PMP_AMATCH_OFF == a_field) {
- return 1;
- }
+ /*
+ * If the PMP entry is not off and the address is in range, do the priv
+ * check
+ */
+ if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
if ((mode != PRV_M) || pmp_is_locked(env, i)) {
allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
--
2.21.0
- [Qemu-riscv] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 01/32] target/riscv: Allow setting ISA extensions via CPU props, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 03/32] target/riscv: Fix PMP range boundary address bug, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 02/32] sifive_prci: Read and write PRCI registers, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 05/32] RISC-V: Only Check PMP if MMU translation succeeds, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 04/32] target/riscv: Implement riscv_cpu_unassigned_access, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 06/32] RISC-V: Raise access fault exceptions on PMP violations, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 07/32] RISC-V: Check for the effective memory privilege mode during PMP checks, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 08/32] RISC-V: Check PMP during Page Table Walks, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 09/32] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 10/32] RISC-V: Fix a PMP check with the correct access size, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 11/32] riscv: virt: Correct pci "bus-range" encoding, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 12/32] RISC-V: Fix a memory leak when realizing a sifive_e, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 13/32] target/riscv: Restructure deprecatd CPUs, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 14/32] target/riscv: Add the privledge spec version 1.11.0, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 17/32] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 15/32] target/riscv: Add the mcountinhibit CSR, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 16/32] target/riscv: Set privledge spec 1.11.0 as default, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 18/32] target/riscv: Require either I or E base extension, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 20/32] target/riscv: Add support for disabling/enabling Counters, Palmer Dabbelt, 2019/07/03