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[PULL v2 05/14] riscv: AND stage-1 and stage-2 protection flags
From: |
Alistair Francis |
Subject: |
[PULL v2 05/14] riscv: AND stage-1 and stage-2 protection flags |
Date: |
Wed, 29 Apr 2020 13:19:57 -0700 |
Take the result of stage-1 and stage-2 page table walks and AND the two
protection flags together. This way we require both to set permissions
instead of just stage-2.
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Tested-by: Anup Patel <address@hidden>
Message-id: address@hidden
Message-Id: <address@hidden>
---
target/riscv/cpu_helper.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index f36d184b7b..50e13a064f 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -707,7 +707,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
#ifndef CONFIG_USER_ONLY
vaddr im_address;
hwaddr pa = 0;
- int prot;
+ int prot, prot2;
bool pmp_violation = false;
bool m_mode_two_stage = false;
bool hs_mode_two_stage = false;
@@ -757,13 +757,15 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
/* Second stage lookup */
im_address = pa;
- ret = get_physical_address(env, &pa, &prot, im_address,
+ ret = get_physical_address(env, &pa, &prot2, im_address,
access_type, mmu_idx, false, true);
qemu_log_mask(CPU_LOG_MMU,
"%s 2nd-stage address=%" VADDR_PRIx " ret %d physical "
TARGET_FMT_plx " prot %d\n",
- __func__, im_address, ret, pa, prot);
+ __func__, im_address, ret, pa, prot2);
+
+ prot &= prot2;
if (riscv_feature(env, RISCV_FEATURE_PMP) &&
(ret == TRANSLATE_SUCCESS) &&
--
2.26.2
- [PULL v2 00/14] RISC-V Patch Queue for 5.1, Alistair Francis, 2020/04/29
- [PULL v2 01/14] riscv/sifive_u: Fix up file ordering, Alistair Francis, 2020/04/29
- [PULL v2 02/14] riscv/sifive_u: Add a serial property to the sifive_u SoC, Alistair Francis, 2020/04/29
- [PULL v2 04/14] riscv: Don't use stage-2 PTE lookup protection flags, Alistair Francis, 2020/04/29
- [PULL v2 03/14] riscv/sifive_u: Add a serial property to the sifive_u machine, Alistair Francis, 2020/04/29
- [PULL v2 07/14] hw/riscv: Generate correct "mmu-type" for 32-bit machines, Alistair Francis, 2020/04/29
- [PULL v2 06/14] riscv: Fix Stage2 SV32 page table walk, Alistair Francis, 2020/04/29
- [PULL v2 05/14] riscv: AND stage-1 and stage-2 protection flags,
Alistair Francis <=
- [PULL v2 09/14] target/riscv: Add a sifive-e34 cpu type, Alistair Francis, 2020/04/29
- [PULL v2 08/14] riscv: sifive_e: Support changing CPU type, Alistair Francis, 2020/04/29
- [PULL v2 12/14] hw/riscv: Add optional symbol callback ptr to riscv_load_firmware(), Alistair Francis, 2020/04/29
- [PULL v2 10/14] linux-user/riscv: fix up struct target_ucontext definition, Alistair Francis, 2020/04/29
- [PULL v2 14/14] hw/riscv/spike: Allow more than one CPUs, Alistair Francis, 2020/04/29
- [PULL v2 13/14] hw/riscv/spike: Allow loading firmware separately using -bios option, Alistair Francis, 2020/04/29
- [PULL v2 11/14] roms: opensbi: Upgrade from v0.6 to v0.7, Alistair Francis, 2020/04/29
- Re: [PULL v2 00/14] RISC-V Patch Queue for 5.1, Peter Maydell, 2020/04/30