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[PULL v2 08/14] riscv: sifive_e: Support changing CPU type
From: |
Alistair Francis |
Subject: |
[PULL v2 08/14] riscv: sifive_e: Support changing CPU type |
Date: |
Wed, 29 Apr 2020 13:20:00 -0700 |
From: Corey Wharton <address@hidden>
Allows the CPU to be changed from the default via the -cpu command
line option.
Signed-off-by: Corey Wharton <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Message-Id: <address@hidden>
[ Changes by AF:
- Set "cpu-type" from the machine and not SoC
]
Signed-off-by: Alistair Francis <address@hidden>
---
hw/riscv/sifive_e.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 646553a7c3..b53109521e 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -123,8 +123,6 @@ static void riscv_sifive_e_soc_init(Object *obj)
object_initialize_child(obj, "cpus", &s->cpus,
sizeof(s->cpus), TYPE_RISCV_HART_ARRAY,
&error_abort, NULL);
- object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type",
- &error_abort);
object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
&error_abort);
sysbus_init_child_obj(obj, "riscv.sifive.e.gpio0",
@@ -141,6 +139,8 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev,
Error **errp)
SiFiveESoCState *s = RISCV_E_SOC(dev);
MemoryRegion *sys_mem = get_system_memory();
+ object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type",
+ &error_abort);
object_property_set_bool(OBJECT(&s->cpus), true, "realized",
&error_abort);
@@ -219,6 +219,7 @@ static void riscv_sifive_e_machine_init(MachineClass *mc)
mc->desc = "RISC-V Board compatible with SiFive E SDK";
mc->init = riscv_sifive_e_init;
mc->max_cpus = 1;
+ mc->default_cpu_type = SIFIVE_E_CPU;
}
DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init)
--
2.26.2
- [PULL v2 00/14] RISC-V Patch Queue for 5.1, Alistair Francis, 2020/04/29
- [PULL v2 01/14] riscv/sifive_u: Fix up file ordering, Alistair Francis, 2020/04/29
- [PULL v2 02/14] riscv/sifive_u: Add a serial property to the sifive_u SoC, Alistair Francis, 2020/04/29
- [PULL v2 04/14] riscv: Don't use stage-2 PTE lookup protection flags, Alistair Francis, 2020/04/29
- [PULL v2 03/14] riscv/sifive_u: Add a serial property to the sifive_u machine, Alistair Francis, 2020/04/29
- [PULL v2 07/14] hw/riscv: Generate correct "mmu-type" for 32-bit machines, Alistair Francis, 2020/04/29
- [PULL v2 06/14] riscv: Fix Stage2 SV32 page table walk, Alistair Francis, 2020/04/29
- [PULL v2 05/14] riscv: AND stage-1 and stage-2 protection flags, Alistair Francis, 2020/04/29
- [PULL v2 09/14] target/riscv: Add a sifive-e34 cpu type, Alistair Francis, 2020/04/29
- [PULL v2 08/14] riscv: sifive_e: Support changing CPU type,
Alistair Francis <=
- [PULL v2 12/14] hw/riscv: Add optional symbol callback ptr to riscv_load_firmware(), Alistair Francis, 2020/04/29
- [PULL v2 10/14] linux-user/riscv: fix up struct target_ucontext definition, Alistair Francis, 2020/04/29
- [PULL v2 14/14] hw/riscv/spike: Allow more than one CPUs, Alistair Francis, 2020/04/29
- [PULL v2 13/14] hw/riscv/spike: Allow loading firmware separately using -bios option, Alistair Francis, 2020/04/29
- [PULL v2 11/14] roms: opensbi: Upgrade from v0.6 to v0.7, Alistair Francis, 2020/04/29
- Re: [PULL v2 00/14] RISC-V Patch Queue for 5.1, Peter Maydell, 2020/04/30