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[PATCH v2 04/16] hw/riscv: Sort machines Kconfig options in alphabetical
From: |
Bin Meng |
Subject: |
[PATCH v2 04/16] hw/riscv: Sort machines Kconfig options in alphabetical order |
Date: |
Wed, 7 Dec 2022 18:03:23 +0800 |
SHAKTI_C machine Kconfig option was inserted in disorder. Fix it.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v1)
hw/riscv/Kconfig | 16 +++++++++-------
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 1e4b58024f..4550b3b938 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -4,6 +4,8 @@ config RISCV_NUMA
config IBEX
bool
+# RISC-V machines in alphabetical order
+
config MICROCHIP_PFSOC
bool
select CADENCE_SDHCI
@@ -22,13 +24,6 @@ config OPENTITAN
select SIFIVE_PLIC
select UNIMP
-config SHAKTI_C
- bool
- select UNIMP
- select SHAKTI_UART
- select RISCV_ACLINT
- select SIFIVE_PLIC
-
config RISCV_VIRT
bool
imply PCI_DEVICES
@@ -50,6 +45,13 @@ config RISCV_VIRT
select FW_CFG_DMA
select PLATFORM_BUS
+config SHAKTI_C
+ bool
+ select RISCV_ACLINT
+ select SHAKTI_UART
+ select SIFIVE_PLIC
+ select UNIMP
+
config SIFIVE_E
bool
select RISCV_ACLINT
--
2.34.1
- [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC, Bin Meng, 2022/12/07
- [PATCH v2 03/16] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC, Bin Meng, 2022/12/07
- [PATCH v2 04/16] hw/riscv: Sort machines Kconfig options in alphabetical order,
Bin Meng <=
- [PATCH v2 05/16] hw/riscv: spike: Remove misleading comments, Bin Meng, 2022/12/07
- [PATCH v2 06/16] hw/intc: sifive_plic: Drop PLICMode_H, Bin Meng, 2022/12/07
- [PATCH v2 08/16] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize(), Bin Meng, 2022/12/07
- [PATCH v2 07/16] hw/intc: sifive_plic: Improve robustness of the PLIC config parser, Bin Meng, 2022/12/07
- [PATCH v2 11/16] hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC, Bin Meng, 2022/12/07
- [PATCH v2 13/16] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb, Bin Meng, 2022/12/07