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Re: [PATCH v2 08/16] hw/intc: sifive_plic: Use error_setg() to propagate
From: |
Alistair Francis |
Subject: |
Re: [PATCH v2 08/16] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize() |
Date: |
Thu, 8 Dec 2022 14:18:32 +1000 |
On Wed, Dec 7, 2022 at 8:06 PM Bin Meng <bmeng@tinylab.org> wrote:
>
> The realize() callback has an errp for us to propagate the error up.
> While we are here, corret the wrong multi-line comment format.
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
>
> ---
>
> Changes in v2:
> - new patch: "hw/intc: sifive_plic: Use error_setg() to propagate the error
> up via errp in sifive_plic_realize()"
>
> hw/intc/sifive_plic.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
> index c9af94a888..9cb4c6d6d4 100644
> --- a/hw/intc/sifive_plic.c
> +++ b/hw/intc/sifive_plic.c
> @@ -379,7 +379,8 @@ static void sifive_plic_realize(DeviceState *dev, Error
> **errp)
> s->m_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts);
> qdev_init_gpio_out(dev, s->m_external_irqs, s->num_harts);
>
> - /* We can't allow the supervisor to control SEIP as this would allow the
> + /*
> + * We can't allow the supervisor to control SEIP as this would allow the
> * supervisor to clear a pending external interrupt which will result in
> * lost a interrupt in the case a PLIC is attached. The SEIP bit must be
> * hardware controlled when a PLIC is attached.
> @@ -387,8 +388,8 @@ static void sifive_plic_realize(DeviceState *dev, Error
> **errp)
> for (i = 0; i < s->num_harts; i++) {
> RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i));
> if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
> - error_report("SEIP already claimed");
> - exit(1);
> + error_setg(errp, "SEIP already claimed");
> + return;
> }
> }
>
> --
> 2.34.1
>
>
- [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC, Bin Meng, 2022/12/07
- [PATCH v2 03/16] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC, Bin Meng, 2022/12/07
- [PATCH v2 04/16] hw/riscv: Sort machines Kconfig options in alphabetical order, Bin Meng, 2022/12/07
- [PATCH v2 05/16] hw/riscv: spike: Remove misleading comments, Bin Meng, 2022/12/07
- [PATCH v2 06/16] hw/intc: sifive_plic: Drop PLICMode_H, Bin Meng, 2022/12/07
- [PATCH v2 08/16] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize(), Bin Meng, 2022/12/07
- [PATCH v2 07/16] hw/intc: sifive_plic: Improve robustness of the PLIC config parser, Bin Meng, 2022/12/07
- [PATCH v2 11/16] hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC, Bin Meng, 2022/12/07
- [PATCH v2 13/16] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb, Bin Meng, 2022/12/07
- [PATCH v2 10/16] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC, Bin Meng, 2022/12/07
- [PATCH v2 12/16] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev", Bin Meng, 2022/12/07
- [PATCH v2 09/16] hw/intc: sifive_plic: Update "num-sources" property default value, Bin Meng, 2022/12/07
- [PATCH v2 14/16] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0, Bin Meng, 2022/12/07
- [PATCH v2 15/16] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization, Bin Meng, 2022/12/07