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[PATCH v3 04/19] target/riscv/cpu.c: restrict 'mimpid' value
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH v3 04/19] target/riscv/cpu.c: restrict 'mimpid' value |
Date: |
Thu, 22 Jun 2023 10:56:45 -0300 |
Following the same logic used with 'mvendorid' let's also restrict
'mimpid' for named CPUs. Generic CPUs keep setting the value freely.
Note that we're getting rid of the default RISCV_CPU_MARCHID value. The
reason is that this is not a good default since it's dynamic, changing
with with every QEMU version, regardless of whether the actual
implementation of the CPU changed from one QEMU version to the other.
Named CPU should set it to a meaningful value instead and generic CPUs
can set whatever they want.
This is the error thrown for an invalid 'mimpid' value for the veyron-v1
CPU:
$ ./qemu-system-riscv64 -M virt -nographic -cpu veyron-v1,mimpid=2
qemu-system-riscv64: can't apply global veyron-v1-riscv-cpu.mimpid=2:
Unable to change veyron-v1-riscv-cpu mimpid (0x111)
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 34 ++++++++++++++++++++++++++++++++--
1 file changed, 32 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b65958a887..33cc28acf1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -42,7 +42,6 @@
#define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \
(QEMU_VERSION_MINOR << 8) | \
(QEMU_VERSION_MICRO))
-#define RISCV_CPU_MIMPID RISCV_CPU_MARCHID
static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
@@ -1739,7 +1738,6 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
- DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID),
#ifndef CONFIG_USER_ONLY
DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC),
@@ -1858,6 +1856,35 @@ static void cpu_get_mvendorid(Object *obj, Visitor *v,
const char *name,
visit_type_bool(v, name, &value, errp);
}
+static void cpu_set_mimpid(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ bool dynamic_cpu = riscv_cpu_is_dynamic(obj);
+ RISCVCPU *cpu = RISCV_CPU(obj);
+ uint64_t prev_val = cpu->cfg.mimpid;
+ uint64_t value;
+
+ if (!visit_type_uint64(v, name, &value, errp)) {
+ return;
+ }
+
+ if (!dynamic_cpu && prev_val != value) {
+ error_setg(errp, "Unable to change %s mimpid (0x%lx)",
+ object_get_typename(obj), prev_val);
+ return;
+ }
+
+ cpu->cfg.mimpid = value;
+}
+
+static void cpu_get_mimpid(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ bool value = RISCV_CPU(obj)->cfg.mimpid;
+
+ visit_type_bool(v, name, &value, errp);
+}
+
static void riscv_cpu_class_init(ObjectClass *c, void *data)
{
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
@@ -1892,6 +1919,9 @@ static void riscv_cpu_class_init(ObjectClass *c, void
*data)
object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid,
cpu_set_mvendorid, NULL, NULL);
+ object_class_property_add(c, "mimpid", "uint64", cpu_get_mimpid,
+ cpu_set_mimpid, NULL, NULL);
+
device_class_set_props(dc, riscv_cpu_properties);
}
--
2.41.0
- [PATCH v3 00/19] target/riscv, KVM: fixes and enhancements, Daniel Henrique Barboza, 2023/06/22
- [PATCH v3 01/19] target/riscv: skip features setup for KVM CPUs, Daniel Henrique Barboza, 2023/06/22
- [PATCH v3 02/19] hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set, Daniel Henrique Barboza, 2023/06/22
- [PATCH v3 03/19] target/riscv/cpu.c: restrict 'mvendorid' value, Daniel Henrique Barboza, 2023/06/22
- [PATCH v3 04/19] target/riscv/cpu.c: restrict 'mimpid' value,
Daniel Henrique Barboza <=
- [PATCH v3 08/19] target/riscv: handle mvendorid/marchid/mimpid for KVM CPUs, Daniel Henrique Barboza, 2023/06/22
- [PATCH v3 05/19] target/riscv/cpu.c: restrict 'marchid' value, Daniel Henrique Barboza, 2023/06/22
- [PATCH v3 10/19] target/riscv/kvm.c: init 'misa_ext_mask' with scratch CPU, Daniel Henrique Barboza, 2023/06/22
- [PATCH v3 07/19] target/riscv: read marchid/mimpid in kvm_riscv_init_machine_ids(), Daniel Henrique Barboza, 2023/06/22
- [PATCH v3 13/19] target/riscv/kvm.c: update KVM MISA bits, Daniel Henrique Barboza, 2023/06/22
- [PATCH v3 12/19] target/riscv: add KVM specific MISA properties, Daniel Henrique Barboza, 2023/06/22