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[PATCH v9 3/6] target/riscv: Add helper functions to calculate current n
From: |
Alexey Baturo |
Subject: |
[PATCH v9 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking |
Date: |
Sat, 11 May 2024 13:10:50 +0300 |
From: Alexey Baturo <baturo.alexey@gmail.com>
Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 5 ++++
target/riscv/cpu_helper.c | 58 +++++++++++++++++++++++++++++++++++++++
2 files changed, 63 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 52b6ba73c8..9cac723b19 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -698,8 +698,13 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
bool riscv_cpu_is_32bit(RISCVCPU *cpu);
+bool riscv_cpu_virt_mem_enabled(CPURISCVState *env);
+RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env);
+int riscv_pm_get_pmlen(RISCVPmPmm pmm);
+
RISCVException riscv_csrr(CPURISCVState *env, int csrno,
target_ulong *ret_value);
+
RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index bf58350669..e4a127ca84 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -142,6 +142,64 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
*pflags = flags;
}
+RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env)
+{
+ int pmm = 0;
+#ifndef CONFIG_USER_ONLY
+ int priv_mode = cpu_address_mode(env);
+ /* Get current PMM field */
+ switch (priv_mode) {
+ case PRV_M:
+ pmm = riscv_cpu_cfg(env)->ext_smmpm ?
+ get_field(env->mseccfg, MSECCFG_PMM) : PMM_FIELD_DISABLED;
+ break;
+ case PRV_S:
+ pmm = riscv_cpu_cfg(env)->ext_smnpm ?
+ get_field(env->menvcfg, MENVCFG_PMM) : PMM_FIELD_DISABLED;
+ break;
+ case PRV_U:
+ pmm = riscv_cpu_cfg(env)->ext_ssnpm ?
+ get_field(env->senvcfg, SENVCFG_PMM) : PMM_FIELD_DISABLED;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+#endif
+ return pmm;
+}
+
+bool riscv_cpu_virt_mem_enabled(CPURISCVState *env)
+{
+ bool virt_mem_en = false;
+#ifndef CONFIG_USER_ONLY
+ int satp_mode = 0;
+ int priv_mode = cpu_address_mode(env);
+ /* Get current PMM field */
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
+ satp_mode = get_field(env->satp, SATP32_MODE);
+ } else {
+ satp_mode = get_field(env->satp, SATP64_MODE);
+ }
+ virt_mem_en = ((satp_mode != VM_1_10_MBARE) && (priv_mode != PRV_M));
+#endif
+ return virt_mem_en;
+}
+
+int riscv_pm_get_pmlen(RISCVPmPmm pmm)
+{
+ switch (pmm) {
+ case PMM_FIELD_DISABLED:
+ return 0;
+ case PMM_FIELD_PMLEN7:
+ return 7;
+ case PMM_FIELD_PMLEN16:
+ return 16;
+ default:
+ g_assert_not_reached();
+ }
+ return -1;
+}
+
#ifndef CONFIG_USER_ONLY
/*
--
2.34.1
- [PATCH v9 1/6] target/riscv: Remove obsolete pointer masking extension code., (continued)
- [PATCH v9 1/6] target/riscv: Remove obsolete pointer masking extension code., Alexey Baturo, 2024/05/11
- [PATCH v9 4/6] target/riscv: Add pointer masking tb flags, Alexey Baturo, 2024/05/11
- [PATCH v9 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension, Alexey Baturo, 2024/05/11
- [PATCH v9 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8, Alexey Baturo, 2024/05/11
- [PATCH v9 5/6] target/riscv: Update address modify functions to take into account pointer masking, Alexey Baturo, 2024/05/11
- [PATCH v9 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking,
Alexey Baturo <=
- Re: [PATCH v9 0/6] Pointer Masking update for Zjpm v1.0, liwei, 2024/05/11
Re: [PATCH v9 0/6] Pointer Masking update for Zjpm v1.0, LIU Zhiwei, 2024/05/13