Re: [PATCH v9 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8

[Alistair Francis]

On Sat, May 11, 2024 at 8:12 PM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> From: Alexey Baturo <baturo.alexey@gmail.com>
>
> Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  target/riscv/cpu.h      |  8 ++++++++
>  target/riscv/cpu_bits.h |  3 +++
>  target/riscv/cpu_cfg.h  |  3 +++
>  target/riscv/csr.c      | 11 +++++++++++
>  target/riscv/machine.c  | 10 +++++++---
>  target/riscv/pmp.c      | 13 ++++++++++---
>  target/riscv/pmp.h      | 11 ++++++-----
>  7 files changed, 48 insertions(+), 11 deletions(-)

This patch generates warnings/errors

include/qemu/compiler.h:70:35: error: invalid operands to binary -
(have ‘uint32_t *’ {aka ‘unsigned int *’} and ‘uint64_t *’ {aka ‘long
unsigned int *’})
   70 | #define type_check(t1,t2) ((t1*)0 - (t2*)0)
      |                                   ^
...
../target/riscv/machine.c:167:9: note: in expansion of macro ‘VMSTATE_UINTTL’
  167 |         VMSTATE_UINTTL(env.menvcfg, RISCVCPU),
      |         ^~~~~~~~~~~~~~

Alistair