Re: [PATCH v9 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm e

qemu-riscv

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v9 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm e

From:	liwei
Subject:	Re: [PATCH v9 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8
Date:	Sat, 11 May 2024 22:16:08 +0800
User-agent:	Mozilla Thunderbird


On 2024/5/11 18:10, Alexey Baturo wrote:

From: Alexey Baturo <baturo.alexey@gmail.com>

Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
  target/riscv/cpu.h      |  8 ++++++++
  target/riscv/cpu_bits.h |  3 +++
  target/riscv/cpu_cfg.h  |  3 +++
  target/riscv/csr.c      | 11 +++++++++++
  target/riscv/machine.c  | 10 +++++++---
  target/riscv/pmp.c      | 13 ++++++++++---
  target/riscv/pmp.h      | 11 ++++++-----
  7 files changed, 48 insertions(+), 11 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 232521bb87..52b6ba73c8 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -121,6 +121,14 @@ typedef enum {
      EXT_STATUS_DIRTY,
  } RISCVExtStatus;

+/* Enum holds PMM field values for Zjpm v0.8 extension */

+typedef enum {
+    PMM_FIELD_DISABLED = 0,
+    PMM_FIELD_RESERVED = 1,
+    PMM_FIELD_PMLEN7   = 2,
+    PMM_FIELD_PMLEN16  = 3,
+} RISCVPmPmm;
+
  #define MMU_USER_IDX 3

#define MAX_RISCV_PMPS (16)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index da16ba236a..13ce2218d1 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -708,6 +708,7 @@ typedef enum RISCVException {
  #define MENVCFG_CBIE                       (3UL << 4)
  #define MENVCFG_CBCFE                      BIT(6)
  #define MENVCFG_CBZE                       BIT(7)
+#define MENVCFG_PMM                        (3ULL << 32)
  #define MENVCFG_ADUE                       (1ULL << 61)
  #define MENVCFG_PBMTE                      (1ULL << 62)
  #define MENVCFG_STCE                       (1ULL << 63)
@@ -721,11 +722,13 @@ typedef enum RISCVException {
  #define SENVCFG_CBIE                       MENVCFG_CBIE
  #define SENVCFG_CBCFE                      MENVCFG_CBCFE
  #define SENVCFG_CBZE                       MENVCFG_CBZE
+#define SENVCFG_PMM                        MENVCFG_PMM

#define HENVCFG_FIOM MENVCFG_FIOM

  #define HENVCFG_CBIE                       MENVCFG_CBIE
  #define HENVCFG_CBCFE                      MENVCFG_CBCFE
  #define HENVCFG_CBZE                       MENVCFG_CBZE
+#define HENVCFG_PMM                        MENVCFG_PMM
  #define HENVCFG_ADUE                       MENVCFG_ADUE
  #define HENVCFG_PBMTE                      MENVCFG_PBMTE
  #define HENVCFG_STCE                       MENVCFG_STCE
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index e1e4f32698..9ecdc792c5 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -120,6 +120,9 @@ struct RISCVCPUConfig {
      bool ext_ssaia;
      bool ext_sscofpmf;
      bool ext_smepmp;
+    bool ext_ssnpm;
+    bool ext_smnpm;
+    bool ext_smmpm;
      bool rvv_ta_all_1s;
      bool rvv_ma_all_1s;

diff --git a/target/riscv/csr.c b/target/riscv/csr.c

index 4b2c932564..45b548eb0b 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -530,6 +530,9 @@ static RISCVException have_mseccfg(CPURISCVState *env, int 
csrno)
      if (riscv_cpu_cfg(env)->ext_zkr) {
          return RISCV_EXCP_NONE;
      }
+    if (riscv_cpu_cfg(env)->ext_smmpm) {
+        return RISCV_EXCP_NONE;
+    }

return RISCV_EXCP_ILLEGAL_INST;

  }
@@ -2083,6 +2086,10 @@ static RISCVException write_menvcfg(CPURISCVState *env, 
int csrno,
                  (cfg->ext_sstc ? MENVCFG_STCE : 0) |
                  (cfg->ext_svadu ? MENVCFG_ADUE : 0);
      }
+    /* Update PMM field only if the value is valid according to Zjpm v0.8 */
+    if (((val & MENVCFG_PMM) >> 32) != PMM_FIELD_RESERVED) {
+        mask |= MENVCFG_PMM;
+    }

Extension and RV64 check seems missed here.This field is added by smnpm,So I think it's can only be changed only when smnpm is enabled.

      env->menvcfg = (env->menvcfg & ~mask) | (val & mask);

return RISCV_EXCP_NONE;

@@ -2127,6 +2134,10 @@ static RISCVException write_senvcfg(CPURISCVState *env, 
int csrno,
                                      target_ulong val)
  {
      uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | 
SENVCFG_CBZE;
+    /* Update PMM field only if the value is valid according to Zjpm v0.8 */
+    if (((val & SENVCFG_PMM) >> 32) != PMM_FIELD_RESERVED) {
+        mask |= SENVCFG_PMM;
+    }
      RISCVException ret

similar to above.

ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);

diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 64ab66e332..bbbb28f373 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -152,15 +152,19 @@ static const VMStateDescription vmstate_vector = {

static bool pointermasking_needed(void *opaque)

  {
-    return false;
+    RISCVCPU *cpu = opaque;
+    return cpu->cfg.ext_ssnpm || cpu->cfg.ext_smnpm || cpu->cfg.ext_smmpm;
  }

static const VMStateDescription vmstate_pointermasking = {

      .name = "cpu/pointer_masking",
-    .version_id = 1,
-    .minimum_version_id = 1,
+    .version_id = 2,
+    .minimum_version_id = 2,
      .needed = pointermasking_needed,
      .fields = (const VMStateField[]) {
+        VMSTATE_UINTTL(env.mseccfg, RISCVCPU),
+        VMSTATE_UINTTL(env.senvcfg, RISCVCPU),
+        VMSTATE_UINTTL(env.menvcfg, RISCVCPU),
          VMSTATE_END_OF_LIST()
      }
  };
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 2a76b611a0..7ddb9dbf0b 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -574,6 +574,12 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t 
addr_index)
  void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
  {
      int i;
+    uint64_t mask = MSECCFG_MMWP | MSECCFG_MML;
+
+    /* Update PMM field only if the value is valid according to Zjpm v0.8 */
+    if (((val & MSECCFG_PMM) >> 32) != PMM_FIELD_RESERVED) {
+        mask |= MSECCFG_PMM;
+    }


similar to above too.

Regards,

Weiwei Li

      trace_mseccfg_csr_write(env->mhartid, val);

@@ -589,12 +595,13 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong val)if (riscv_cpu_cfg(env)->ext_smepmp) {

          /* Sticky bits */
-        val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
-        if ((val ^ env->mseccfg) & (MSECCFG_MMWP | MSECCFG_MML)) {
+        val |= (env->mseccfg & mask);
+        if ((val ^ env->mseccfg) & mask) {
              tlb_flush(env_cpu(env));
          }
      } else {
-        val &= ~(MSECCFG_MMWP | MSECCFG_MML | MSECCFG_RLB);
+        mask |= MSECCFG_RLB;
+        val &= ~(mask);
      }

env->mseccfg = val;

diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index f5c10ce85c..ccff0eb9b6 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -40,11 +40,12 @@ typedef enum {
  } pmp_am_t;

typedef enum {

-    MSECCFG_MML   = 1 << 0,
-    MSECCFG_MMWP  = 1 << 1,
-    MSECCFG_RLB   = 1 << 2,
-    MSECCFG_USEED = 1 << 8,
-    MSECCFG_SSEED = 1 << 9
+    MSECCFG_MML       = 1 << 0,
+    MSECCFG_MMWP      = 1 << 1,
+    MSECCFG_RLB       = 1 << 2,
+    MSECCFG_USEED     = 1 << 8,
+    MSECCFG_SSEED     = 1 << 9,
+    MSECCFG_PMM       = 3UL << 32,
  } mseccfg_field_t;

typedef struct {

[Prev in Thread]

Current Thread

[Next in Thread]

[PATCH v9 0/6] Pointer Masking update for Zjpm v1.0, Alexey Baturo, 2024/05/11
- [PATCH v9 1/6] target/riscv: Remove obsolete pointer masking extension code., Alexey Baturo, 2024/05/11
- [PATCH v9 4/6] target/riscv: Add pointer masking tb flags, Alexey Baturo, 2024/05/11
  - Re: [PATCH v9 4/6] target/riscv: Add pointer masking tb flags, LIU Zhiwei, 2024/05/13
- [PATCH v9 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension, Alexey Baturo, 2024/05/11
  - Re: [PATCH v9 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension, LIU Zhiwei, 2024/05/13
- [PATCH v9 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8, Alexey Baturo, 2024/05/11
  - Re: [PATCH v9 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8, liwei <=
  - Re: [PATCH v9 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8, Alistair Francis, 2024/05/13
- [PATCH v9 5/6] target/riscv: Update address modify functions to take into account pointer masking, Alexey Baturo, 2024/05/11
  - Re: [PATCH v9 5/6] target/riscv: Update address modify functions to take into account pointer masking, LIU Zhiwei, 2024/05/13
- [PATCH v9 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking, Alexey Baturo, 2024/05/11
  - Re: [PATCH v9 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking, LIU Zhiwei, 2024/05/13
  - Re: [PATCH v9 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking, LIU Zhiwei, 2024/05/13
    - Re: [PATCH v9 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking, LIU Zhiwei, 2024/05/13
- Re: [PATCH v9 0/6] Pointer Masking update for Zjpm v1.0, liwei, 2024/05/11
  - Re: [PATCH v9 0/6] Pointer Masking update for Zjpm v1.0, Alistair Francis, 2024/05/13
    - Re: [PATCH v9 0/6] Pointer Masking update for Zjpm v1.0, Alexey Baturo, 2024/05/13

Prev by Date: Re: [PATCH 1/5] target/riscv: Reuse the conversion function of priv_spec and string
Next by Date: Re: [PATCH 2/5] target/riscv: Support the version for ss1p13
Previous by thread: [PATCH v9 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8
Next by thread: Re: [PATCH v9 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8
Index(es):
- Date
- Thread