Re: [PATCH] target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule

[Alistair Francis]

On Sun, Aug 25, 2024 at 3:34 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Gitlab issue [1] reports a misleading error when trying to run a 'rv64'
> cpu with 'zfinx' and without 'f':
>
> $ ./build/qemu-system-riscv64 -nographic -M virt -cpu rv64,zfinx=true,f=false
> qemu-system-riscv64: Zfinx cannot be supported together with F extension
>
> The user explicitly disabled F and the error message mentions a conflict
> with Zfinx and F.
>
> The problem isn't the error reporting, but the logic used when applying
> the implied ZFA rule that enables RVF unconditionally, without honoring
> user choice (i.e. keep F disabled).
>
> Change cpu_enable_implied_rule() to check if the user deliberately
> disabled a MISA bit. In this case we shouldn't either re-enable the bit
> nor apply any implied rules related to it.
>
> After this change the error message now shows:
>
> $ ./build/qemu-system-riscv64 -nographic -M virt -cpu rv64,zfinx=true,f=false
> qemu-system-riscv64: Zfa extension requires F extension
>
> Disabling 'zfa':
>
> $ ./build/qemu-system-riscv64 -nographic -M virt -cpu 
> rv64,zfinx=true,f=false,zfa=false
> qemu-system-riscv64: D extension requires F extension
>
> And finally after disabling 'd':
>
> $ ./build/qemu-system-riscv64 -nographic -M virt -cpu 
> rv64,zfinx=true,f=false,zfa=false,d=false
> (OpenSBI boots ...)
>
> [1] https://gitlab.com/qemu-project/qemu/-/issues/2486
>
> Cc: Frank Chang <frank.chang@sifive.com>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2486
> Fixes: 047da861f9 ("target/riscv: Introduce extension implied rule helpers")
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Thanks!

Applied to riscv-to-apply.next

Alistair