[RFC PATCH 3/7] target/riscv: Add riscv big endian data flag into DisasContext

[Roan Richmond]

Allows for endian check on load/store instructions. Keeps the BE_DATA
flag in sync with the MSTATUS MBE value.

Authored-by: Roan Richmond <roan.richmond@codethink.co.uk>
Co-authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Co-authored-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
---
 target/riscv/cpu.h                      | 2 ++
 target/riscv/cpu_helper.c               | 1 +
 target/riscv/insn_trans/trans_rvi.c.inc | 6 ++++++
 target/riscv/translate.c                | 3 +++
 4 files changed, 12 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 284b112821..18c3a2ed6b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -637,6 +637,8 @@ FIELD(TB_FLAGS, FCFI_ENABLED, 28, 1)
 FIELD(TB_FLAGS, FCFI_LP_EXPECTED, 29, 1)
 /* zicfiss needs a TB flag so that correct TB is located based on tb flags */
 FIELD(TB_FLAGS, BCFI_ENABLED, 30, 1)
+/* Indicates Big Endian (BE) data */
+FIELD(TB_FLAGS, BE_DATA, 31, 1)
 
 #ifdef TARGET_RISCV32
 #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 0a3ead69ea..6271c9b887 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -206,6 +206,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
     }
 #endif
 
+    flags = FIELD_DP32(flags, TB_FLAGS, BE_DATA, !!(env->mstatus & 
MSTATUS_MBE));
     flags = FIELD_DP32(flags, TB_FLAGS, FS, fs);
     flags = FIELD_DP32(flags, TB_FLAGS, VS, vs);
     flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc 
b/target/riscv/insn_trans/trans_rvi.c.inc
index 96c218a9d7..76bb233a37 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -326,6 +326,9 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp 
memop)
     if (ctx->cfg_ptr->ext_zama16b) {
         memop |= MO_ATOM_WITHIN16;
     }
+
+    memop |= ctx->be_data;
+
     decode_save_opc(ctx, 0);
     if (get_xl(ctx) == MXL_RV128) {
         out = gen_load_i128(ctx, a, memop);
@@ -427,6 +430,9 @@ static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp 
memop)
     if (ctx->cfg_ptr->ext_zama16b) {
         memop |= MO_ATOM_WITHIN16;
     }
+
+    memop |= ctx->be_data;
+
     decode_save_opc(ctx, 0);
     if (get_xl(ctx) == MXL_RV128) {
         return gen_store_i128(ctx, a, memop);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index bccaf8e89a..d1c8ac7fa8 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -121,6 +121,8 @@ typedef struct DisasContext {
     bool fcfi_lp_expected;
     /* zicfiss extension, if shadow stack was enabled during TB gen */
     bool bcfi_enabled;
+    /* If set to Big Endian data mode */
+    MemOp be_data;
 } DisasContext;
 
 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -1255,6 +1257,7 @@ static void riscv_tr_init_disas_context(DisasContextBase 
*dcbase, CPUState *cs)
     ctx->zero = tcg_constant_tl(0);
     ctx->virt_inst_excp = false;
     ctx->decoders = cpu->decoders;
+    ctx->be_data = FIELD_EX32(tb_flags, TB_FLAGS, BE_DATA) ? MO_BE : MO_LE;
 }
 
 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
-- 
2.43.0