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[RFC PATCH 2/7] target/riscv: Add SSTATUS_UBE
From: |
Roan Richmond |
Subject: |
[RFC PATCH 2/7] target/riscv: Add SSTATUS_UBE |
Date: |
Fri, 20 Dec 2024 15:45:30 +0000 |
From: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Adds the UBE flag for SSTATUS this a read-only mirror of
MSTATUS UBE.
Authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Co-authored-by: Ben Dooks <ben.dooks@codethink.co.uk>
Co-authored-by: Roan Richmond <roan.richmond@codethink.co.uk>
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 6 ++++--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 2cc12a06b6..6d8e4eaf32 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -583,6 +583,7 @@ typedef enum {
#define SSTATUS_SIE 0x00000002
#define SSTATUS_UPIE 0x00000010
#define SSTATUS_SPIE 0x00000020
+#define SSTATUS_UBE 0x00000040
#define SSTATUS_SPP 0x00000100
#define SSTATUS_VS 0x00000600
#define SSTATUS_FS 0x00006000
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 0ee4614bf1..5e7933dea0 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -2980,7 +2980,8 @@ static RISCVException read_sstatus_i128(CPURISCVState
*env, int csrno,
static RISCVException read_sstatus(CPURISCVState *env, int csrno,
target_ulong *val)
{
- target_ulong mask = (sstatus_v1_10_mask);
+ // Allow reading from SSTATUS_UBE
+ target_ulong mask = sstatus_v1_10_mask | SSTATUS_UBE;
if (env->xl != MXL_RV32 || env->debugger) {
mask |= SSTATUS64_UXL;
}
@@ -2997,7 +2998,8 @@ static RISCVException read_sstatus(CPURISCVState *env,
int csrno,
static RISCVException write_sstatus(CPURISCVState *env, int csrno,
target_ulong val)
{
- target_ulong mask = (sstatus_v1_10_mask);
+ // Disallow writing to SSTATUS_UBE as read-only
+ target_ulong mask = (sstatus_v1_10_mask) & (~SSTATUS_UBE);
if (env->xl != MXL_RV32 || env->debugger) {
if ((val & SSTATUS64_UXL) != 0) {
--
2.43.0
- [RFC PATCH 0/7] Add RISCV big endian support, Roan Richmond, 2024/12/20
- [RFC PATCH 1/7] target/riscv: Add riscv MSTATUS_xBE CSR support, Roan Richmond, 2024/12/20
- [RFC PATCH 2/7] target/riscv: Add SSTATUS_UBE,
Roan Richmond <=
- [RFC PATCH 7/7] target/riscv: Add big endian CPU target, Roan Richmond, 2024/12/20
- [RFC PATCH 5/7] target/riscv: Add big endian check for atomic ops, Roan Richmond, 2024/12/20
- [RFC PATCH 3/7] target/riscv: Add riscv big endian data flag into DisasContext, Roan Richmond, 2024/12/20
- [RFC PATCH 6/7] taregt/riscv: Add big endian checks for pagetable, Roan Richmond, 2024/12/20
- [RFC PATCH 4/7] target/riscv: Add sfence.vma for endian change, Roan Richmond, 2024/12/20