Re: [Qemu-devel] [RFC] QOMification of AXI streams

[Edgar E. Iglesias]

On Thu, Jun 14, 2012 at 12:16:45PM +1000, Benjamin Herrenschmidt wrote:
> On Thu, 2012-06-14 at 04:03 +0200, Edgar E. Iglesias wrote:
> > Thanks for the clarificatino Ben.
> > 
> > I don't know much about PCI but in the embedded world I've never seen
> > anything that resemblems what you describe. Devices at the bottom of
> > the hierharcy (or at any location) that make acceses to the memory system
> > do it through a different port located at a differnt logical position in
> > the hierarchy. 
> 
> Right, that's what I meant when I said that master and slave interfaces
> don't have to be the same, but that's not a problem. A given device
> could depend on two memory regions, one for downstream accesses only and
> one for upstream accesses, both located in different positions in the
> hierarchy.
> 
> > In fact, a DMA ctrl can through it's master port access it's
> > slave port without it even noticing that it is the same device accessing
> > itself and the access will travel top-down through the bus hierarchy.
> 
> That sometimes work ... and sometimes doesn't ... some combinations of
> busses/devices will not allow that, some will deadlock, it really
> depends on the setup.
> 
> > I've never seen address decoding beeing done in reverse.. bottom-up.
> 
> It really depends on the bus type and happens on embedded as well.
> 
> If your device master "port" is directly on the processor bus, you still
> have to deal with sibling devices potentially decoding right ? Now, what
> about you have a bridge from that bus to another bus. For example ppc
> PLB to AXI (that stuff exist out on the field).
> 
> An AXI device might issue a cycle on the AXI portion, that can be
> decoded by either a sibling AXI device ... or go up. In most cases

No, it doesn't really go up.. This is where we disagree.


> though, "upstream" is some kind of substractive decoding (ie. anything
> -not- decoded by a sibling goes up).

I've never seen this happen, but I won't say it doesn't exist because
you'll find all kinds of HW out there that'll do all kind of stuff
you wouldn't imagine.


> 
> This gets even more obvious with PCI of course. Then add a b43 wifi card
> on PCI, you have AXI -> PCI -> SSB (silicon backplane). Now what happens
> when one of the sub-devices on SBB (the MAC interface for example) does
> a bus master ? You have at least 2 layers to cross before you hit your
> processor bus. 
> 
> Add iommu's to the soup and you get into a serious mess :-)

IOmmus messify things a bit, but the translation is only done from
the masters above the iommu going down theough the iommu. Not
vice versa. At least AFAIK.

Cheers