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Re: [Qemu-devel] [PATCH 04/24] target-arm: Log bad system register acces
From: |
Peter Crosthwaite |
Subject: |
Re: [Qemu-devel] [PATCH 04/24] target-arm: Log bad system register accesses with LOG_UNIMP |
Date: |
Sat, 25 Jan 2014 09:30:25 +1000 |
On Wed, Jan 22, 2014 at 6:12 AM, Peter Maydell <address@hidden> wrote:
> Log guest attempts to access unimplemented system registers via
> the LOG_UNIMP reporting mechanism (for both the 32 bit and 64 bit
> instruction sets). This is particularly useful for debugging
> problems where the guest is trying to use a system register that
> QEMU doesn't implement.
>
> Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
> ---
> target-arm/translate-a64.c | 7 ++++++-
> target-arm/translate.c | 13 +++++++++++++
> 2 files changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
> index a808a88..e0f6765 100644
> --- a/target-arm/translate-a64.c
> +++ b/target-arm/translate-a64.c
> @@ -1121,7 +1121,12 @@ static void handle_sys(DisasContext *s, uint32_t insn,
> bool isread,
> crn, crm, op0, op1, op2));
>
> if (!ri) {
> - /* Unknown register */
> + /* Unknown register; this might be a guest error or a QEMU
> + * unimplemented feature.
> + */
> + qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch64 "
> + "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
> + isread ? "read" : "write", op0, op1, crn, crm, op2);
> unallocated_encoding(s);
> return;
> }
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 8d240e1..59a206d 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -6672,6 +6672,19 @@ static int disas_coproc_insn(CPUARMState * env,
> DisasContext *s, uint32_t insn)
> return 0;
> }
>
> + /* Unknown register; this might be a guest error or a QEMU
> + * unimplemented feature.
> + */
> + if (is64) {
> + qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 "
> + "64 bit system register cp:%d opc1: %d crm:%d\n",
> + isread ? "read" : "write", cpnum, opc1, crm);
> + } else {
> + qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 "
> + "system register cp:%d opc1:%d crn:%d crm:%d
> opc2:%d\n",
> + isread ? "read" : "write", cpnum, opc1, crn, crm,
> opc2);
> + }
> +
> return 1;
> }
>
> --
> 1.8.5
>
>
- [Qemu-devel] [PATCH 02/24] target-arm: Define names for SCTLR bits, (continued)
- [Qemu-devel] [PATCH 02/24] target-arm: Define names for SCTLR bits, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 08/24] target-arm: A64: Implement MSR (immediate) instructions, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 24/24] target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 20/24] target-arm: Implement AArch64 MPIDR, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 13/24] target-arm: Implement AArch64 TLB invalidate ops, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 17/24] target-arm: Implement AArch64 TCR_EL1, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 04/24] target-arm: Log bad system register accesses with LOG_UNIMP, Peter Maydell, 2014/01/21
- Re: [Qemu-devel] [PATCH 04/24] target-arm: Log bad system register accesses with LOG_UNIMP,
Peter Crosthwaite <=
- [Qemu-devel] [PATCH 19/24] target-arm: Implement AArch64 TTBR*, Peter Maydell, 2014/01/21
- Re: [Qemu-devel] [PATCH 19/24] target-arm: Implement AArch64 TTBR*, Peter Maydell, 2014/01/28
[Qemu-devel] [PATCH 21/24] target-arm: Implement AArch64 generic timers, Peter Maydell, 2014/01/21
[Qemu-devel] [PATCH 14/24] target-arm: Implement AArch64 dummy MDSCR_EL1, Peter Maydell, 2014/01/21
[Qemu-devel] [PATCH 07/24] target-arm: A64: Make cache ID registers visible to AArch64, Peter Maydell, 2014/01/21