[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH 12/17] target-openrisc: Enable m[tf]spr from use
|
From: |
Richard Henderson |
|
Subject: |
Re: [Qemu-devel] [PATCH 12/17] target-openrisc: Enable m[tf]spr from user mode |
|
Date: |
Mon, 14 Sep 2015 10:11:01 -0700 |
|
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 |
On 09/13/2015 01:34 AM, Bastian Koppelmann wrote:
> Looking at the article, user mode seems to be optional, so I'm not against it,
> but it does look weird. How does ork1sim do it?
It's haphazard. There are checks for supervisor in the l_mtspr and l_mfspr
insns, but not other uses of the sprs, such as l_rfe.
In the meantime, testing of the multiply-accumulate instructions is hindered by
the fact that linux-user can't read the MACHI and MACLO special registers.
r~
- [Qemu-devel] [PATCH 07/17] target-openrisc: Keep SR_CY and SR_OV in a separate variables, (continued)
- [Qemu-devel] [PATCH 07/17] target-openrisc: Keep SR_CY and SR_OV in a separate variables, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH 13/17] target-openrisc: Enable trap, csync, msync, psync for user mode, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH 10/17] target-openrisc: Represent MACHI:MACLO as a single unit, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH 12/17] target-openrisc: Enable m[tf]spr from user mode, Richard Henderson, 2015/09/02
[Qemu-devel] [PATCH 11/17] target-openrisc: Rationalize immediate extraction, Richard Henderson, 2015/09/02
[Qemu-devel] [PATCH 15/17] target-openrisc: Fix madd, Richard Henderson, 2015/09/02
[Qemu-devel] [PATCH 14/17] target-openrisc: Implement muld, muldu, macu, msbu, Richard Henderson, 2015/09/02
[Qemu-devel] [PATCH 17/17] target-openrisc: Implement lwa, swa, Richard Henderson, 2015/09/02
[Qemu-devel] [PATCH 16/17] target-openrisc: Write back result before FPE exception, Richard Henderson, 2015/09/02