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[Qemu-devel] [PATCH 21/28] target/riscv: Replace gen_store() with trans_
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PATCH 21/28] target/riscv: Replace gen_store() with trans_store() |
Date: |
Fri, 12 Oct 2018 19:30:40 +0200 |
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as gen_store() did.
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>
---
target/riscv/insn_trans/trans_rvi.inc.c | 31 ++++++++++++++++------
target/riscv/translate.c | 34 -------------------------
2 files changed, 23 insertions(+), 42 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c
b/target/riscv/insn_trans/trans_rvi.inc.c
index 873a5e8b53..b09c52a708 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -192,27 +192,42 @@ static bool trans_ld(DisasContext *ctx, arg_ld *a,
uint32_t insn)
#endif
}
-static bool trans_sb(DisasContext *ctx, arg_sb *a, uint32_t insn)
+static bool trans_store(DisasContext *ctx, arg_sb *a, int memop)
{
- gen_store(ctx, OPC_RISC_SB, a->rs1, a->rs2, a->imm);
+ TCGv t0 = tcg_temp_new();
+ TCGv dat = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_get_gpr(dat, a->rs2);
+
+ if (memop < 0) {
+ return false;
+ }
+
+ tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
+ tcg_temp_free(t0);
+ tcg_temp_free(dat);
return true;
}
+
+static bool trans_sb(DisasContext *ctx, arg_sb *a, uint32_t insn)
+{
+ return trans_store(ctx, a, MO_SB);
+}
static bool trans_sh(DisasContext *ctx, arg_sh *a, uint32_t insn)
{
- gen_store(ctx, OPC_RISC_SH, a->rs1, a->rs2, a->imm);
- return true;
+ return trans_store(ctx, a, MO_TESW);
}
+
static bool trans_sw(DisasContext *ctx, arg_sw *a, uint32_t insn)
{
- gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm);
- return true;
+ return trans_store(ctx, a, MO_TESL);
}
static bool trans_sd(DisasContext *ctx, arg_sd *a, uint32_t insn)
{
#ifdef TARGET_RISCV64
- gen_store(ctx, OPC_RISC_SD, a->rs1, a->rs2, a->imm);
- return true;
+ return trans_store(ctx, a, MO_TEQ);
#else
return false;
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 544e71a46c..feae31cb94 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -54,20 +54,6 @@ typedef struct DisasContext {
int frm;
} DisasContext;
-/* convert riscv funct3 to qemu memop for load/store */
-static const int tcg_memop_lookup[8] = {
- [0 ... 7] = -1,
- [0] = MO_SB,
- [1] = MO_TESW,
- [2] = MO_TESL,
- [4] = MO_UB,
- [5] = MO_TEUW,
-#ifdef TARGET_RISCV64
- [3] = MO_TEQ,
- [6] = MO_TEUL,
-#endif
-};
-
#ifdef TARGET_RISCV64
#define CASE_OP_32_64(X) case X: case glue(X, W)
#else
@@ -488,26 +474,6 @@ static void gen_jal(CPURISCVState *env, DisasContext *ctx,
int rd,
ctx->base.is_jmp = DISAS_NORETURN;
}
-static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
- target_long imm)
-{
- TCGv t0 = tcg_temp_new();
- TCGv dat = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- tcg_gen_addi_tl(t0, t0, imm);
- gen_get_gpr(dat, rs2);
- int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
-
- if (memop < 0) {
- gen_exception_illegal(ctx);
- return;
- }
-
- tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
- tcg_temp_free(t0);
- tcg_temp_free(dat);
-}
-
static void gen_set_rm(DisasContext *ctx, int rm)
{
TCGv_i32 t0;
--
2.19.1
- [Qemu-devel] [PATCH 09/28] target/riscv: Convert RV64A insns to decodetree, (continued)
- [Qemu-devel] [PATCH 09/28] target/riscv: Convert RV64A insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 26/28] target/riscv: Remove gen_system(), Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 15/28] target/riscv: Convert quadrant 0 of RVXC insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 24/28] target/riscv: Remove shift and slt insn manual decoding, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 27/28] target/riscv: Remove decode_RV32_64G(), Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 21/28] target/riscv: Replace gen_store() with trans_store(),
Bastian Koppelmann <=
- [Qemu-devel] [PATCH 25/28] target/riscv: Remove manual decoding of RV32/64M insn, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 19/28] target/riscv: Replace gen_branch() with trans_branch(), Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 23/28] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 28/28] target/riscv: Replace gen_exception_illegal with return false, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 13/28] target/riscv: Convert RV64D insns to decodetree, Bastian Koppelmann, 2018/10/12