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Re: [Qemu-devel] [PATCH 21/28] target/riscv: Replace gen_store() with tr
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From: |
Richard Henderson |
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Subject: |
Re: [Qemu-devel] [PATCH 21/28] target/riscv: Replace gen_store() with trans_store() |
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Date: |
Sat, 13 Oct 2018 12:45:08 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.0 |
On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
> +static bool trans_store(DisasContext *ctx, arg_sb *a, int memop)
gen_store.
> {
> - gen_store(ctx, OPC_RISC_SB, a->rs1, a->rs2, a->imm);
> + TCGv t0 = tcg_temp_new();
> + TCGv dat = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> + tcg_gen_addi_tl(t0, t0, a->imm);
> + gen_get_gpr(dat, a->rs2);
> +
> + if (memop < 0) {
> + return false;
> + }
Can't happen. Otherwise,
Reviewed-by: Richard Henderson <address@hidden>
r~
- Re: [Qemu-devel] [PATCH 09/28] target/riscv: Convert RV64A insns to decodetree, (continued)
- [Qemu-devel] [PATCH 26/28] target/riscv: Remove gen_system(), Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 15/28] target/riscv: Convert quadrant 0 of RVXC insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 24/28] target/riscv: Remove shift and slt insn manual decoding, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 27/28] target/riscv: Remove decode_RV32_64G(), Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 21/28] target/riscv: Replace gen_store() with trans_store(), Bastian Koppelmann, 2018/10/12
- Re: [Qemu-devel] [PATCH 21/28] target/riscv: Replace gen_store() with trans_store(),
Richard Henderson <=
- [Qemu-devel] [PATCH 25/28] target/riscv: Remove manual decoding of RV32/64M insn, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 19/28] target/riscv: Replace gen_branch() with trans_branch(), Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 23/28] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 28/28] target/riscv: Replace gen_exception_illegal with return false, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 13/28] target/riscv: Convert RV64D insns to decodetree, Bastian Koppelmann, 2018/10/12