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[Qemu-devel] [PATCH 23/28] target/riscv: make ADD/SUB/OR/XOR/AND insn us
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PATCH 23/28] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists |
Date: |
Fri, 12 Oct 2018 19:30:42 +0200 |
manual decoding in gen_arith() is not necessary with decodetree.
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>
---
target/riscv/insn32.decode | 3 ++-
target/riscv/insn_trans/trans_rvi.inc.c | 21 ++++++----------
target/riscv/translate.c | 33 ++++++++++++++-----------
3 files changed, 27 insertions(+), 30 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 806315b830..549cacfdd5 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -40,6 +40,7 @@
# Argument sets:
&branch imm rs2 rs1
&arith_imm imm rs1 rd
+&arith rd rs1 rs2
&shift shamt rs1 rd
&atomic aq rl rs2 rs1 rd
@@ -48,7 +49,7 @@
@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1
@sfence_vm ....... ..... ..... ... ..... ....... %rs1
address@hidden ....... ..... ..... ... ..... .......
%rs2 %rs1 %rd
address@hidden ....... ..... ..... ... ..... ....... &arith
%rs2 %rs1 %rd
@i ............ ..... ... ..... ....... &arith_imm imm=%imm_i %rs1
%rd
@b ....... ..... ..... ... ..... ....... &branch imm=%imm_b %rs2 %rs1
@s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c
b/target/riscv/insn_trans/trans_rvi.inc.c
index 76d4baab69..cb0c6263bd 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -323,14 +323,12 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a,
uint32_t insn)
static bool trans_add(DisasContext *ctx, arg_add *a, uint32_t insn)
{
- gen_arith(ctx, OPC_RISC_ADD, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_add_tl);
}
static bool trans_sub(DisasContext *ctx, arg_sub *a, uint32_t insn)
{
- gen_arith(ctx, OPC_RISC_SUB, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_sub_tl);
}
static bool trans_sll(DisasContext *ctx, arg_sll *a, uint32_t insn)
@@ -353,8 +351,7 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a,
uint32_t insn)
static bool trans_xor(DisasContext *ctx, arg_xor *a, uint32_t insn)
{
- gen_arith(ctx, OPC_RISC_XOR, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_xor_tl);
}
static bool trans_srl(DisasContext *ctx, arg_srl *a, uint32_t insn)
@@ -371,14 +368,12 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a,
uint32_t insn)
static bool trans_or(DisasContext *ctx, arg_or *a, uint32_t insn)
{
- gen_arith(ctx, OPC_RISC_OR, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_or_tl);
}
static bool trans_and(DisasContext *ctx, arg_and *a, uint32_t insn)
{
- gen_arith(ctx, OPC_RISC_AND, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_and_tl);
}
static bool trans_addiw(DisasContext *ctx, arg_addiw *a, uint32_t insn)
@@ -436,8 +431,7 @@ static bool trans_addw(DisasContext *ctx, arg_addw *a,
uint32_t insn)
gen_exception_illegal(ctx);
return true;
#endif
- gen_arith(ctx, OPC_RISC_ADDW, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_add_tl);
}
static bool trans_subw(DisasContext *ctx, arg_subw *a, uint32_t insn)
@@ -446,8 +440,7 @@ static bool trans_subw(DisasContext *ctx, arg_subw *a,
uint32_t insn)
gen_exception_illegal(ctx);
return true;
#endif
- gen_arith(ctx, OPC_RISC_SUBW, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_sub_tl);
}
static bool trans_sllw(DisasContext *ctx, arg_sllw *a, uint32_t insn)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index ed1d93af47..92aa4641b0 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -175,12 +175,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int
rd, int rs1,
gen_get_gpr(source2, rs2);
switch (opc) {
- CASE_OP_32_64(OPC_RISC_ADD):
- tcg_gen_add_tl(source1, source1, source2);
- break;
- CASE_OP_32_64(OPC_RISC_SUB):
- tcg_gen_sub_tl(source1, source1, source2);
- break;
#if defined(TARGET_RISCV64)
case OPC_RISC_SLLW:
tcg_gen_andi_tl(source2, source2, 0x1F);
@@ -197,9 +191,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int
rd, int rs1,
case OPC_RISC_SLTU:
tcg_gen_setcond_tl(TCG_COND_LTU, source1, source1, source2);
break;
- case OPC_RISC_XOR:
- tcg_gen_xor_tl(source1, source1, source2);
- break;
#if defined(TARGET_RISCV64)
case OPC_RISC_SRLW:
/* clear upper 32 */
@@ -225,12 +216,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int
rd, int rs1,
tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
tcg_gen_sar_tl(source1, source1, source2);
break;
- case OPC_RISC_OR:
- tcg_gen_or_tl(source1, source1, source2);
- break;
- case OPC_RISC_AND:
- tcg_gen_and_tl(source1, source1, source2);
- break;
CASE_OP_32_64(OPC_RISC_MUL):
tcg_gen_mul_tl(source1, source1, source2);
break;
@@ -473,6 +458,24 @@ static bool trans_arith_imm(DisasContext *ctx,
arg_arith_imm *a,
return true;
}
+static bool trans_arith(DisasContext *ctx, arg_arith *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv source1, source2;
+ source1 = tcg_temp_new();
+ source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ (*func)(source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
/* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c"
#include "insn_trans/trans_rvm.inc.c"
--
2.19.1
- [Qemu-devel] [PATCH 24/28] target/riscv: Remove shift and slt insn manual decoding, (continued)
- [Qemu-devel] [PATCH 24/28] target/riscv: Remove shift and slt insn manual decoding, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 27/28] target/riscv: Remove decode_RV32_64G(), Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 21/28] target/riscv: Replace gen_store() with trans_store(), Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 25/28] target/riscv: Remove manual decoding of RV32/64M insn, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 19/28] target/riscv: Replace gen_branch() with trans_branch(), Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 23/28] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists,
Bastian Koppelmann <=
- [Qemu-devel] [PATCH 28/28] target/riscv: Replace gen_exception_illegal with return false, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 13/28] target/riscv: Convert RV64D insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 12/28] target/riscv: Convert RV32D insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 20/28] target/riscv: Replace gen_load() with trans_load(), Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 22/28] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Bastian Koppelmann, 2018/10/12