Re: [Qemu-devel] [PATCH 15/28] target/riscv: Convert quadrant 0 of RVXC insns to decodetree

[Bastian Koppelmann]

On 10/13/18 8:18 PM, Richard Henderson wrote:
> On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
> > +# Argument sets:
> > +&cl               rs1 rd
> > +&cl_dw     uimm   rs1 rd
> > +&ciw       nzuimm     rd
> > +&cs               rs1 rs2
> > +&cs_dw     uimm   rs1 rs2
> I guess this is good enough for now.
> What I'd like to see is something like
>
> &i  imm rs1 rd      !extern


That looks so much better. Can you CC me when you send the patches for 
the extern support, so I can implement this for RISC-V?


Cheers,

Bastian