Re: [Simulavr-devel] attiny85 - external interrupt support (INT0/PCINT)

[Graziano Previato]

Hi Thomas,

first of all thanks for you notice and for your effort!


Just to keep you informed at the same time I've finished my 'USI' module. 
If (and I have to underline if... I'm actually doing some tests) it will 
work as planned, it's emulating the whole USI module as per specs in ATTiny 
Atmel datasheet, including fronts, latches and timing, with the only 
exception of two things: the 'retard' of 50~300 nsec in the start detector 
and the USIDC.

I'm looking to introduce the retard, but I don't have enough knowledge on 
the pin module to implement the USIDC.

To have it working I have made some (very little...) changes on the hwport 
and the pin modules.


Now I'm in the test phase.

I'm not very confident with git (and also with c++...). If you want a copy 
of the module let me know.



Ciao,

--gra


--On February 7, 2016 at 5:58:11 PM +0100 Thomas K <address@hidden> 
wrote:

> Hi Graziano,
>
> I've now pushed my changes for USI.
>
> > I have supposed that the problem of PINS management was already solved
> > by the pins module... But could be I'm wrong...
>
> Yes ... and no. You'll see it. Pin class itself isn't the problem.
> Problem is output control on HWPort.
>
> > I have developed a software module for a protocol that is in a middle
> > between a 'LIN' and a OneWire... and I need to test it at least to
> > understand if the multi-master features are working... I'm using the
> > full USI feature...
>
> Using the USI as UART (I assume, that this is the case for you) should
> work, but in the moment I haven't a test code for that to check it.
> (especially if real life behaviour is equal to simulated behaviour)
>
> cu, Thomas
>
> _______________________________________________
> Simulavr-devel mailing list
> address@hidden
> https://lists.nongnu.org/mailman/listinfo/simulavr-devel