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Re: [Qemu-arm] [Qemu-devel] [PATCH v2 11/32] arm/translate-a64: add FP16
From: |
Richard Henderson |
Subject: |
Re: [Qemu-arm] [Qemu-devel] [PATCH v2 11/32] arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16 |
Date: |
Thu, 8 Feb 2018 12:54:36 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 |
On 02/08/2018 09:31 AM, Alex Bennée wrote:
> Signed-off-by: Alex Bennée <address@hidden>
> ---
> target/arm/helper-a64.c | 49
> ++++++++++++++++++++++++++++++++++++++++++++++
> target/arm/helper-a64.h | 5 +++++
> target/arm/translate-a64.c | 15 ++++++++++++++
> 3 files changed, 69 insertions(+)
>
> diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
> index 25e45121af..78eeda31d1 100644
> --- a/target/arm/helper-a64.c
> +++ b/target/arm/helper-a64.c
> @@ -599,3 +599,52 @@ ADVSIMD_HALFOP(min)
> ADVSIMD_HALFOP(max)
> ADVSIMD_HALFOP(minnum)
> ADVSIMD_HALFOP(maxnum)
> +
> +/*
> + * Floating point comparisons produce an integer result. Softfloat
> + * routines return float_relation types which we convert to the 0/-1
> + * Neon requires.
> + */
> +
> +#define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0
> +
> +uint32_t HELPER(advsimd_ceq_f16)(float16 a, float16 b, void *fpstp)
> +{
> + float_status *fpst = fpstp;
> + int compare = float16_compare_quiet(a, b, fpst);
> + return ADVSIMD_CMPRES(compare == float_relation_equal);
Not using float16_eq etc?
> +}
> +
> +uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
> +{
> + float_status *fpst = fpstp;
> + int compare = float16_compare(a, b, fpst);
> + return ADVSIMD_CMPRES(compare == float_relation_greater ||
> + compare == float_relation_equal);
Especially float16_le(b, a, fpst).
Otherwise,
Reviewed-by: Richard Henderson <address@hidden>
r~
- [Qemu-arm] [PATCH v2 02/32] target/arm/cpu64: introduce ARM_V8_FP16 feature bit, (continued)
- [Qemu-arm] [PATCH v2 02/32] target/arm/cpu64: introduce ARM_V8_FP16 feature bit, Alex Bennée, 2018/02/08
- [Qemu-arm] [PATCH v2 06/32] target/arm/helper: pass explicit fpst to set_rmode, Alex Bennée, 2018/02/08
- [Qemu-arm] [PATCH v2 08/32] arm/translate-a64: handle_3same_64 comment fix, Alex Bennée, 2018/02/08
- [Qemu-arm] [PATCH v2 05/32] target/arm/cpu.h: add additional float_status flags, Alex Bennée, 2018/02/08
- [Qemu-arm] [PATCH v2 10/32] arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16, Alex Bennée, 2018/02/08
- [Qemu-arm] [PATCH v2 11/32] arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16, Alex Bennée, 2018/02/08
- Re: [Qemu-arm] [Qemu-devel] [PATCH v2 11/32] arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16,
Richard Henderson <=
- [Qemu-arm] [PATCH v2 09/32] arm/translate-a64: initial decode for simd_three_reg_same_fp16, Alex Bennée, 2018/02/08
- [Qemu-arm] [PATCH v2 07/32] arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV), Alex Bennée, 2018/02/08
- [Qemu-arm] [PATCH v2 12/32] arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16, Alex Bennée, 2018/02/08
- [Qemu-arm] [PATCH v2 13/32] arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16, Alex Bennée, 2018/02/08