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[RFC v3 36/71] target/riscv: rvv-1.0: register gather instructions
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From: |
frank . chang |
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Subject: |
[RFC v3 36/71] target/riscv: rvv-1.0: register gather instructions |
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Date: |
Thu, 6 Aug 2020 18:46:33 +0800 |
From: Frank Chang <frank.chang@sifive.com>
* Add vrgatherei16.vv instruction.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 4 ++
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 21 ++++++++--
target/riscv/vector_helper.c | 53 ++++++++++++++-----------
4 files changed, 52 insertions(+), 27 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index a5d58010134..35fb09d2892 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1105,6 +1105,10 @@ DEF_HELPER_6(vrgather_vv_b, void, ptr, ptr, ptr, ptr,
env, i32)
DEF_HELPER_6(vrgather_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vrgather_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vrgather_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vrgatherei16_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vrgatherei16_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vrgatherei16_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vrgatherei16_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vrgather_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vrgather_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vrgather_vx_w, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 15afc469cb0..67306ac7161 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -609,6 +609,7 @@ vslidedown_vx 001111 . ..... ..... 100 ..... 1010111 @r_vm
vslidedown_vi 001111 . ..... ..... 011 ..... 1010111 @r_vm
vslide1down_vx 001111 . ..... ..... 110 ..... 1010111 @r_vm
vrgather_vv 001100 . ..... ..... 000 ..... 1010111 @r_vm
+vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm
vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm
vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm
vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 469d0bad056..6698e1e860b 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -3308,7 +3308,21 @@ static bool vrgather_vv_check(DisasContext *s, arg_rmrr
*a)
require_vm(a->vm, a->rd);
}
+static bool vrgatherei16_vv_check(DisasContext *s, arg_rmrr *a)
+{
+ float emul = 16.0 / (1 << (s->sew + 3)) * s->flmul;
+ return require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ (emul >= 0.125 && emul <= 8) &&
+ require_align(a->rd, s->flmul) &&
+ require_align(a->rs1, emul) &&
+ require_align(a->rs2, s->flmul) &&
+ (a->rd != a->rs2 && a->rd != a->rs1) &&
+ require_vm(a->vm, a->rd);
+}
+
GEN_OPIVV_TRANS(vrgather_vv, vrgather_vv_check)
+GEN_OPIVV_TRANS(vrgatherei16_vv, vrgatherei16_vv_check)
static bool vrgather_vx_check(DisasContext *s, arg_rmrr *a)
{
@@ -3328,11 +3342,11 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr
*a)
}
if (a->vm && s->vl_eq_vlmax) {
- int vlmax = s->vlen;
+ int vlmax = s->vlen * s->flmul / (1 << (s->sew + 3));
TCGv_i64 dest = tcg_temp_new_i64();
if (a->rs1 == 0) {
- vec_element_loadi(s, dest, a->rs2, 0);
+ vec_element_loadi(s, dest, a->rs2, 0, false);
} else {
vec_element_loadx(s, dest, a->rs2, cpu_gpr[a->rs1], vlmax);
}
@@ -3359,7 +3373,8 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr
*a)
}
if (a->vm && s->vl_eq_vlmax) {
- if (a->rs1 >= s->vlen) {
+ int vlmax = s->vlen * s->flmul / (1 << (s->sew + 3));
+ if (a->rs1 >= vlmax) {
tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), 0);
} else {
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 13ce6f33a9e..d7827a9db10 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4711,33 +4711,38 @@ GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, uint32_t, H4)
GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8)
/* Vector Register Gather Instruction */
-#define GEN_VEXT_VRGATHER_VV(NAME, ETYPE, H) \
-void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
- CPURISCVState *env, uint32_t desc) \
-{ \
- uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \
- uint32_t vm = vext_vm(desc); \
- uint32_t vl = env->vl; \
- uint32_t index, i; \
- \
- for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, i)) { \
- continue; \
- } \
- index = *((ETYPE *)vs1 + H(i)); \
- if (index >= vlmax) { \
- *((ETYPE *)vd + H(i)) = 0; \
- } else { \
- *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(index)); \
- } \
- } \
+#define GEN_VEXT_VRGATHER_VV(NAME, TS1, TS2, HS1, HS2) \
+void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t vlmax = vext_max_elems(desc, sizeof(TS1), false); \
+ uint32_t vm = vext_vm(desc); \
+ uint32_t vl = env->vl; \
+ uint32_t index, i; \
+ \
+ for (i = 0; i < vl; i++) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
+ continue; \
+ } \
+ index = *((TS1 *)vs1 + HS1(i)); \
+ if (index >= vlmax) { \
+ *((TS2 *)vd + HS2(i)) = 0; \
+ } else { \
+ *((TS2 *)vd + HS2(i)) = *((TS2 *)vs2 + HS2(index)); \
+ } \
+ } \
}
/* vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; */
-GEN_VEXT_VRGATHER_VV(vrgather_vv_b, uint8_t, H1)
-GEN_VEXT_VRGATHER_VV(vrgather_vv_h, uint16_t, H2)
-GEN_VEXT_VRGATHER_VV(vrgather_vv_w, uint32_t, H4)
-GEN_VEXT_VRGATHER_VV(vrgather_vv_d, uint64_t, H8)
+GEN_VEXT_VRGATHER_VV(vrgather_vv_b, uint8_t, uint8_t, H1, H1)
+GEN_VEXT_VRGATHER_VV(vrgather_vv_h, uint16_t, uint16_t, H2, H2)
+GEN_VEXT_VRGATHER_VV(vrgather_vv_w, uint32_t, uint32_t, H4, H4)
+GEN_VEXT_VRGATHER_VV(vrgather_vv_d, uint64_t, uint64_t, H8, H8)
+
+GEN_VEXT_VRGATHER_VV(vrgatherei16_vv_b, uint16_t, uint8_t, H2, H1)
+GEN_VEXT_VRGATHER_VV(vrgatherei16_vv_h, uint16_t, uint16_t, H2, H2)
+GEN_VEXT_VRGATHER_VV(vrgatherei16_vv_w, uint16_t, uint32_t, H2, H4)
+GEN_VEXT_VRGATHER_VV(vrgatherei16_vv_d, uint16_t, uint64_t, H2, H8)
#define GEN_VEXT_VRGATHER_VX(NAME, ETYPE, H) \
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
--
2.17.1
- Re: [RFC v3 26/71] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, (continued)
- [RFC v3 28/71] target/riscv: rvv-1.0: floating-point square-root instruction, frank . chang, 2020/08/06
- [RFC v3 27/71] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, frank . chang, 2020/08/06
- [RFC v3 29/71] target/riscv: rvv-1.0: floating-point classify instructions, frank . chang, 2020/08/06
- [RFC v3 32/71] target/riscv: rvv-1.0: set-X-first mask bit instructions, frank . chang, 2020/08/06
- [RFC v3 30/71] target/riscv: rvv-1.0: mask population count instruction, frank . chang, 2020/08/06
- [RFC v3 31/71] target/riscv: rvv-1.0: find-first-set mask bit instruction, frank . chang, 2020/08/06
- [RFC v3 33/71] target/riscv: rvv-1.0: iota instruction, frank . chang, 2020/08/06
- [RFC v3 34/71] target/riscv: rvv-1.0: element index instruction, frank . chang, 2020/08/06
- [RFC v3 35/71] target/riscv: rvv-1.0: allow load element with sign-extended, frank . chang, 2020/08/06
- [RFC v3 36/71] target/riscv: rvv-1.0: register gather instructions,
frank . chang <=
- [RFC v3 38/71] target/riscv: rvv-1.0: floating-point move instruction, frank . chang, 2020/08/06
- [RFC v3 39/71] target/riscv: rvv-1.0: floating-point scalar move instructions, frank . chang, 2020/08/06
- [RFC v3 37/71] target/riscv: rvv-1.0: integer scalar move instructions, frank . chang, 2020/08/06
- [RFC v3 40/71] target/riscv: rvv-1.0: whole register move instructions, frank . chang, 2020/08/06
- [RFC v3 41/71] target/riscv: rvv-1.0: integer extension instructions, frank . chang, 2020/08/06
- [RFC v3 42/71] target/riscv: rvv-1.0: single-width averaging add and subtract instructions, frank . chang, 2020/08/06
- [RFC v3 43/71] target/riscv: rvv-1.0: single-width bit shift instructions, frank . chang, 2020/08/06
- [RFC v3 44/71] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow, frank . chang, 2020/08/06
- [RFC v3 45/71] target/riscv: rvv-1.0: narrowing integer right shift instructions, frank . chang, 2020/08/06
- [RFC v3 46/71] target/riscv: rvv-1.0: widening integer multiply-add instructions, frank . chang, 2020/08/06