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[RFC v3 43/71] target/riscv: rvv-1.0: single-width bit shift instruction
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From: |
frank . chang |
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Subject: |
[RFC v3 43/71] target/riscv: rvv-1.0: single-width bit shift instructions |
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Date: |
Thu, 6 Aug 2020 18:46:40 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.inc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 68634298fa5..a22db5f2f13 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1901,9 +1901,9 @@ GEN_OPIVX_GVEC_SHIFT_TRANS(vsll_vx, shls)
GEN_OPIVX_GVEC_SHIFT_TRANS(vsrl_vx, shrs)
GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx, sars)
-GEN_OPIVI_GVEC_TRANS(vsll_vi, IMM_ZX, vsll_vx, shli)
-GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_ZX, vsrl_vx, shri)
-GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_ZX, vsra_vx, sari)
+GEN_OPIVI_GVEC_TRANS(vsll_vi, IMM_TRUNC_SEW, vsll_vx, shli)
+GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_TRUNC_SEW, vsrl_vx, shri)
+GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_TRUNC_SEW, vsra_vx, sari)
/* Vector Narrowing Integer Right Shift Instructions */
static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
--
2.17.1
- [RFC v3 33/71] target/riscv: rvv-1.0: iota instruction, (continued)
- [RFC v3 33/71] target/riscv: rvv-1.0: iota instruction, frank . chang, 2020/08/06
- [RFC v3 34/71] target/riscv: rvv-1.0: element index instruction, frank . chang, 2020/08/06
- [RFC v3 35/71] target/riscv: rvv-1.0: allow load element with sign-extended, frank . chang, 2020/08/06
- [RFC v3 36/71] target/riscv: rvv-1.0: register gather instructions, frank . chang, 2020/08/06
- [RFC v3 38/71] target/riscv: rvv-1.0: floating-point move instruction, frank . chang, 2020/08/06
- [RFC v3 39/71] target/riscv: rvv-1.0: floating-point scalar move instructions, frank . chang, 2020/08/06
- [RFC v3 37/71] target/riscv: rvv-1.0: integer scalar move instructions, frank . chang, 2020/08/06
- [RFC v3 40/71] target/riscv: rvv-1.0: whole register move instructions, frank . chang, 2020/08/06
- [RFC v3 41/71] target/riscv: rvv-1.0: integer extension instructions, frank . chang, 2020/08/06
- [RFC v3 42/71] target/riscv: rvv-1.0: single-width averaging add and subtract instructions, frank . chang, 2020/08/06
- [RFC v3 43/71] target/riscv: rvv-1.0: single-width bit shift instructions,
frank . chang <=
- [RFC v3 44/71] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow, frank . chang, 2020/08/06
- [RFC v3 45/71] target/riscv: rvv-1.0: narrowing integer right shift instructions, frank . chang, 2020/08/06
- [RFC v3 46/71] target/riscv: rvv-1.0: widening integer multiply-add instructions, frank . chang, 2020/08/06
- [RFC v3 47/71] target/riscv: rvv-1.0: add Zvqmac extension, frank . chang, 2020/08/06
- [RFC v3 48/71] target/riscv: rvv-1.0: quad-widening integer multiply-add instructions, frank . chang, 2020/08/06
- [RFC v3 49/71] target/riscv: rvv-1.0: single-width saturating add and subtract instructions, frank . chang, 2020/08/06
- [RFC v3 51/71] target/riscv: use softfloat lib float16 comparison functions, frank . chang, 2020/08/06
- [RFC v3 50/71] target/riscv: rvv-1.0: integer comparison instructions, frank . chang, 2020/08/06
- [RFC v3 52/71] target/riscv: rvv-1.0: floating-point compare instructions, frank . chang, 2020/08/06
- [RFC v3 53/71] target/riscv: rvv-1.0: mask-register logical instructions, frank . chang, 2020/08/06